Method of manufacturing an inverter device

• US 7,487,581 B2
• Filed: 03/22/2007
• Issued: 02/10/2009
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tada, Nobumitsu, Obu, Toshiharu, Yoshioka, Shimpei, Sekiya, Hiroki, Hagiwara, Keizo
• Primary Examiner(s): Kim; Paul D
• Application Number:
  US11/723,826
• Publication Number:
  US 20070165383A1
• Time in Patent Office: 691 Days
• Field of Search: 294/17, 295/921, 296/021, 297/40, 297/41, 297/42, 297/59, 298/31, 298/32, 219 68- 70, 361/704, 361/707, 361/717, 363/141, 363/144
• US Class Current: 29/602.1
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/53178 Chip component
• CPC Class Codes: Y10T 29/53183 Multilead component
• CPC Class Codes: Y10T 29/53261 Means to align and advance work part

Abstract

By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor said first conductor and second conductor are connected connected to said wide conductor; and a cooler to which through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.

Claims

1. A method of manufacturing an inverter device that includes a plurality of heat buffer plates, comprising:

bonding a plurality of semiconductor chips and said heat buffer plates by a low melting point or high melting point solder;

bonding said heat buffer plates and a conductor by a low melting point or high melting point solder;

dividing a wide conductor into a plurality of chips fixing said conductor to a cooler;

fixing said heat buffer plates with said plurality of chips;

fixing said conductor and said cooler by application of pressure at locations where the plurality of semiconductor chips are not bonded to said conductor;

forming said conductor as an upper arm conductor and a lower arm conductor; and

bonding a first subset of said heat buffer plates onto said upper arm conductor and bonding a second subset of said heat buffer plates onto said lower arm conductor.

2. The method of manufacturing an inverter device according to claim 1, wherein said fixing of said conductor to said cooler comprises adhesively fixing said conductor to said cooler by means of a ceramics-containing insulating resin sheet.

3. The method of manufacturing an inverter device according to claim 1, wherein the bonding of the plurality of semiconductor chips and the heat buffer plates comprises bonding a top surface of the plurality of semiconductor chips to the heat buffer plates.

4. The method of manufacturing an inverter device according to claim 1, wherein said forming step further comprises:

forming said lower conductor arm to have a first extension part and a second extension part extending in a longitudinal direction substantially parallel with respect to each other and separated from each other by a gap,

wherein a first subset of said plurality of chips are bonded to said second subset of heat buffer plates and are disposed on said lower conductor arm so as to span the gap, and

wherein a second subset of said plurality of chips are bonded to said first subset of heat buffer plates.