Removal of charged defects from metal oxide-gate stacks

• US 7,488,656 B2
• Filed: 04/29/2005
• Issued: 02/10/2009
• Est. Priority Date: 04/29/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Haight, Richard A., Guha, Supratik, Narayanan, Vijay, Cartier, Eduard A., Copel, Matthew W., McFeely, Fenton R.
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US11/119,310
• Publication Number:
  US 20060246740A1
• Time in Patent Office: 1,383 Days
• Field of Search: None
• US Class Current: 438/287
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack. The present invention also provides a semiconductor structure that includes at least one gate stack that has a threshold voltage within a control range and has good carrier mobility.

Claims

1. A method of re-oxidizing a high k gate dielectric of a material stack useful as a pFET to substantially remove charged defects therefrom comprising:

exposing a material stack including a gate dielectric having a dielectric constant of about 4.0 or greater to dilute oxygen at a temperature from about 250°

C. to about 450°

C. for a time period from about 1 minute to about 24 hours, said dilute oxygen has a partial pressure of 100 Torr or less.

2. The method of claim 1 wherein said temperature is from about 300°

C. to about 400°

C. and said time period is from about 10 to about 60 minutes.

3. The method of claim 1 wherein said dilute oxygen has a concentration from about 1 to about 100 ppm.

4. The method of claim 1 wherein said dilute oxygen includes an oxygen source that is diluted with an inert gas.

5. The method of claim 1 wherein said exposing to dilute oxygen is employed as a step in a replacement gate process for fabricating a pFET device.

6. The method of claim 5 wherein said replacement gate process includes providing at least one patterned material stack including said gate dielectric, a metal contact, a metal barrier and polysilicon on a surface of a semiconductor substrate;

forming a planarized dielectric on said semiconductor substrate including atop said at least one patterned gate stack;

removing the polysilicon from said at least one patterned material stack to expose the metal barrier, and then performing said exposing step.

7. The method of claim 1 wherein said exposing to dilute oxygen is performed on a structure that includes at least one patterned material stack including said gate dielectric, a metal contact, a metal barrier and polysilicon on a surface of a semiconductor substrate, said at least one patterned material stack including at least one spacer that is transparent to oxygen or no spacers.

8. The method of claim 7 further comprising at least one other patterned material stack that includes at least one spacer that is oxygen blocking.

9. The method of claim 1 wherein said exposing to dilute oxygen is performed on a structure including a barrier material that includes at least one opening that is located on a surface of a semiconductor substrate that includes at least one isolation region as well as at least one patterned material stack including said gate dielectric, a metal contact, a metal barrier and polysilicon on said substrate, whereby said dilute oxygen enters via the opening using the at least one isolation region as an oxygen pathway.

10. A method of re-oxidizing a high k gate dielectric of a material stack useful as a pFET to substantially remove charged defects therefrom comprising:

exposing a material stack including an oxygen diffusion barrier layer covering a gate dielectric having a dielectric constant of about 4.0 or greater to dilute oxygen at a temperature from about 250°

C. to about 450°

C. for a time period from about 1 minute to about 24 hours, said dilute oxygen has a partial pressure of 100 Torr or less.