Stressed semiconductor device structures having granular semiconductor material

• US 7,488,658 B2
• Filed: 09/13/2006
• Issued: 02/10/2009
• Est. Priority Date: 11/14/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Boyd, Diane C., Chidambarrao, Dureseti, Doris, Bruce B., Belyansky, Michael P., Gluschenkov, Oleg
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US11/531,372
• Publication Number:
  US 20080064172A1
• Time in Patent Office: 881 Days
• Field of Search: None
• US Class Current: 438/296
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Claims

1. A method for fabricating a semiconductor device structure, comprising:

providing a substrate;

forming an nFET and a pFET on the substrate;

replacing portions of the gate electrodes from the nFET and said pFET with a small grained polysilicon;

covering the small-grained polysilicon of the nFET, and then heating the nFET and the pFET, so that an average diameter of the grains within the nFET is less than an average diameter of the grains within the pFET.

2. The method as claimed in claim 1, wherein said step of heating includes heating the nFET and the pFET to temperatures within a range of approximately 500°

C. to approximately 600°

C. for approximately one hour.

3. The method as claimed in claim 1, wherein the small-grained polysilicon has an average grain size in a range of about five nm to about 30 nm.

4. The method as claimed in claim 1, wherein said step of replacing includes removing the portions of the gate electrodes to form recesses, and then disposing the grained polysilicon within the nFET and pFET recesses.

5. The method as claimed in claim 1, wherein said step of replacing includes removing the entire portions of the gate electrodes to form recesses, and then depositing the small-grained polysilicon within the recesses.

6. The method as claimed in claim 1, wherein said step of covering includes disposing a mask over the grained polysilicon of the nFET, the mask consisting essentially of SiN.

7. The method as claimed in claim 1, further comprising forming spacers for the nFET and the pFET, the spacers having different heights.

8. The method as claimed in claim 1, further comprising providing spacers for the mFET and the pFET, the spacers for the pFET having heights which are less than heights of the spacers for the nFET.