Method to make markers for double gate SOI processing

• US 7,488,669 B2
• Filed: 03/16/2005
• Issued: 02/10/2009
• Est. Priority Date: 03/17/2004
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), Koninklijke Philips N.V.
• Inventors: Laidler, David William, Ponomarev, Youri V., Loo, Josine Johanna Gerarda Petra
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US11/083,356
• Publication Number:
  US 20050214985A1
• Time in Patent Office: 1,427 Days
• Field of Search: 438/401, 438/455, 438/462, 257/797, 257/E21.561
• US Class Current: 438/462
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Claims

1. A method of making at least one marker for double gate SOI processing on a SOI wafer,

wherein the SOI wafer comprises a substrate, an oxidized layer on the substrate, and a semiconductor layer on top of the oxidized layer;

wherein the double gate SOI processing is performed on at least one die;

wherein the at least one die is located on the semiconductor layer and comprises at least an inner area arranged as a circuit area and an outer area arranged as scribe line area;

wherein the double gate SOI processing comprises;

separating the semiconductor layer from the oxidized layer, and

attaching the separated semiconductor layer as a turned-over semiconductor layer on a surface of a new substrate, wherein the original top surface of the semiconductor layer is directed towards the surface of the new substrate,

the method of making the at least one marker comprising;

forming a first marker in a first direction in the scribe line area, said first marker having a diffraction structure wherein said diffraction structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in said first direction; and

forming a second marker in the first direction in the scribe line area, the second marker being a mirror image of the first marker, around a second direction perpendicular to said first direction.

2. The method according to claim 1, further comprising choosing a position of the second marker in the scribe line area along the first direction to be mirror-symmetrical with respect to the position of the first marker along the first direction, wherein choosing the position comprises choosing the position of the second marker to be the mirror image of the first marker around a mirror line, the mirror line being a symmetry line of the rectangular envelope of the die in the second direction.

3. The method according to claim 1, wherein the second marker is created in a same lithographic step as the first marker.

4. The method according to claim 3, wherein the semiconductor layer comprises a backside, and wherein the method further comprises a fully aligned processing of the backside of the semiconductor layer using lithographic alignment on the second marker.

5. The method according to claim 1, wherein the new substrate is one of a non-Si substrate and a Si substrate with a high resistivity.

6. The method according to claim 4, wherein the fully aligned processing comprises:

forming at least one component of a heat sink, an RE device, a memory device, an analog device, or a high-voltage device.

7. The method according to claim 4, wherein the fully aligned processing comprises:

forming at least one component of an opto-electronic device.

8. The method according to claim 4, wherein the fully aligned processing comprises:

forming at least one component of a micro-mechanic device.