Thin film semiconductor device and fabrication method therefor

• US 7,488,980 B2
• Filed: 09/15/2004
• Issued: 02/10/2009
• Est. Priority Date: 09/18/2003
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Itoga, Takashi, Ogawa, Yasuyuki, Takafuji, Yutaka
• Primary Examiner(s): Nguyen; Cuong Q
• Application Number:
  US10/940,735
• Publication Number:
  US 20050067619A1
• Time in Patent Office: 1,609 Days
• Field of Search: 257 64- 75, 257347-354
• US Class Current: 257/64
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A relaying pad is formed in a predetermined portion in an insulation layer of the single-crystal thin film device, in a region where the single-crystal thin film device is formed. The relaying pad is for providing connection wiring through the insulator substrate. With this configuration it is possible to prevent an increase in an aspect ratio of a contact hole formed in an insulation layer in a region in which a transferred device is formed, the semiconductor device including a substrate on which the transferred device and a deposited device coexist.

Claims

1. A thin film semiconductor device, comprising:

an insulator substrate including (i) a single-crystal thin film device having an active layer made of a single-crystal silicon, and (ii) a non-single-crystal silicon thin film device having an active layer made of a non-single-crystal silicon;

a contact hole, and

a relaying pad formed in a predetermined portion in an insulation layer of the single-crystal thin film device, in a region where the single-crystal thin film device is formed,

the relaying pad being connected, via the contact hole, with metal wiring or its equivalent wiring which is connected with a predetermined position of a single-crystal layer of the single-crystal thin film device.

2. The thin film semiconductor device as set forth in claim 1, wherein the relaying pad is connected with metal wiring of the non-single-crystal silicon thin film device.

3. The thin film semiconductor device as set forth in claim 1, wherein:

the relaying pad is formed in a layer in which a gate electrode of the single-crystal thin film device is formed.

4. The thin film semiconductor device as set forth in claim 1, wherein:

the relaying pad is formed in a layer in which the active layer of the single-crystal thin film device is formed.

5. The thin film semiconductor device as set forth in claim 1, wherein the relaying pad is formed in a layer in which an active layer or a gate layer of the single-crystal thin film device is formed, and the relaying pad is connected via the contact holes with the metal wirings of different layers above and below the relaying pad.

6. The thin film semiconductor device as set forth in claim 1, wherein:

the contact hole is formed below a source or a drain in the single-crystal thin film device; and

the contact hole is formed above a source or a drain in the non-single-crystal silicon thin film device.