Thin film transistor array panel for a liquid crystal display

• US 7,488,996 B2
• Filed: 06/28/2005
• Issued: 02/10/2009
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chang, Jong-Woong
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US11/168,886
• Publication Number:
  US 20050237812A1
• Time in Patent Office: 1,323 Days
• Field of Search: 257/208, 257/210, 257/691, 257/758, 257/59, 257/72, 257/203, 257/207
• US Class Current: 257/208
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a plurality of gate lines formed on the insulating substrate, each gate line including a pad for connection to an external device;

a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and

a plurality of conductors respectively overlapping at least one of the gate lines and the data lines,

wherein capacitance between the gate lines or the data lines and the conductors decreases as a length of the gate lines or the data lines increases.

2. The thin film transistor array panel of claim 1, wherein each data line comprises a pad portion including the pad, a display portion and a fan-out portion connecting the display portion and the pad portion, and resistance per unit length of the fan-out portion of the data line decrease as a length of the fan-out portion of the data line increases.

3. The thin film transistor array panel of claim 1, wherein each gate line comprises a pad portion including the pad, a display portion and a fan-out portion connecting the display portion and the pad portion, and resistance per unit length of the fan-out portion of the gate line decrease as a length of the fan-out portion of the gate line increases.

4. The thin film transistor array panel of claim 1, wherein the conductors are applied with a reference voltage.

5. The thin film transistor array panel of claim 1, further comprising a pixel electrode located on a pixel area defined by intersections of the gate lines and the data lines, wherein the conductors are formed substantially in a same layer and of a same material as the pixel electrode.

6. The thin film transistor array panel of claim 1, wherein the conductors overlap the gate lines, wherein the conductors are formed substantially in a same layer and of a same material as the data lines.

7. The thin film transistor array panel of claim 1, wherein the conductors overlap the data lines, wherein the conductors are formed substantially in a same layer and of a same material as the gate lines.

8. The thin film transistor array panel of claim 1, wherein the conductors include first conductive segments overlapping the gate lines and second conductive segments overlapping the data lines, the first conductive segments are formed substantially in a same layer and of a same material as the data lines, and the second conductive segments are formed substantially in a same layer and of a same material as the gate lines.

9. The thin film transistor array panel of claim 1, wherein the conductors are floated.

10. A thin film transistor array panel comprising:

an insulating substrate;

a plurality of gate lines formed on the insulating substrate, each gate line including a pad for connection to an external device;

a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and

a plurality of conductors respectively overlapping at least one of the gate lines and the data lines,

wherein overlapping area between the gate lines or the data lines and the conductors decreases as a length of the gate lines or the data lines increases.

11. The thin film transistor array panel of claim 10, wherein each data line comprises a pad portion including the pad, a display portion and a fan-out portion connecting the display portion and the pad portion, and resistance per unit length of the fan-out portion of the data line decrease as a length of the fan-out portion of the data line increases.

12. The thin film transistor array panel of claim 10, wherein each gate line comprises a pad portion including the pad, a display portion and a fan-out portion connecting the display portion and the pad portion, and resistance per unit length of the fan-out portion of the gate line decrease as a length of the fan-out portion of the gate line increases.

13. The thin film transistor array panel of claim 10, wherein the conductors are applied with a reference voltage.

14. The thin film transistor array panel of claim 10, further comprising a pixel electrode located on a pixel area defined by intersections of the gate lines and the data lines, wherein the conductors are formed substantially in a same layer and of a same material as the pixel electrode.

15. The thin film transistor array panel of claim 10, wherein the conductors overlap the gate lines, wherein the conductors are formed substantially in a same layer and of a same material as the data lines.

16. The thin film transistor array panel of claim 10, wherein the conductors overlap the data lines, wherein the conductors are formed substantially in a same layer and of a same material as the gate lines.

17. The thin film transistor array panel of claim 10, wherein the conductors include first conductive segments overlapping the gate lines and second conductive segments overlapping the data lines, the first conductive segments are formed substantially in a same layer and of a same material as the data lines, and the second conductive segments are formed substantially in a same layer and of a same material as the gate lines.

18. The thin film transistor array panel of claim 10, wherein the conductors are floated.