Multi-port memory devices

• US 7,489,164 B2
• Filed: 11/19/2007
• Issued: 02/10/2009
• Est. Priority Date: 05/17/2004
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Raminda Udaya Madurawe
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/986,025
• Publication Number:
  US 20080106953A1
• Time in Patent Office: 449 Days
• Field of Search: 326/40, 326/46, 36518904-18905, 365/230.05
• US Class Current: 326/40
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element, wherein reading the generated signal protects data stored at the storage element from a read condition disturbance.

Claims

1. A semiconductor storage device, comprising:

a storage element to store a data state coupled to ground and a first supply voltage;

an isolation circuit coupled to the storage element comprising an output derived by the stored data state, the isolation circuit further coupled to ground and a second supply voltage lower than the first supply voltage;

a first access device coupled to the storage element and further coupled to a first access circuit to read or alter the stored data state at ground or the first supply voltage;

a second access device coupled to the output and further coupled to a second access circuit to read the output state at ground or the second supply voltage, wherein the isolation circuit prevents the second access circuit from altering the stored data state.

2. The device of claim 1, wherein the storage element comprises one or more elements selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, thin film transistor (TFT).

3. The device of claim 1, wherein the latch state can be altered using the first access device and the first access circuit, and the altered state can be verified using the second access device and the second access circuit concurrently.

4. The device of claim 1, wherein the storage element is selected from the group consisting of volatile or non volatile storage elements.

5. The device of claim 1, wherein the storage element is selected from a group of fuse links, latches, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, Carbon nano-tubes, voltage modulating element, and ferro-electric elements.

6. The device of claim 1, wherein the isolation circuit further comprises one or more elements selected from the following:

diode, transistor, resistor, capacitor, thin film diode, thin film resistor, thin film capacitor, and thin film transistor (TFT).

7. The device of claim 1, wherein the isolation circuit further comprises one or more of:

inverters, buffers, voltage converters, capacitors, resistors, and transistors.

8. The device of claim 1, wherein the isolation circuit is further coupled to a power supply voltage and a ground supply voltage, and wherein the output is driven to said power or ground supply voltage by the stored data state.

9. The device of claim 1, wherein the output is further coupled to a programmable logic circuit.

10. The device of claim 9, wherein the programmable logic circuit comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, NAND logic OR logic, NOR logic, arithmetic logic, carry logic, floating point logic, and any other logic.

11. A three-dimensional semiconductor device, comprising:

a latch to store a data state coupled to a first supply voltage; and

an isolation circuit coupled to the latch and further coupled to a second supply voltage; and

an access device coupled to the isolation circuit and further coupled to an evaluation circuit, wherein the latch data is fully isolated from the evaluation circuit during one mode of operation, and wherein the latch operates at the first supply voltage and the evaluation circuit operates at the second supply voltage lower than the first supply voltage.

12. The device of claim 11, wherein the isolation circuit comprises:

an input coupled to the latch; and

an output coupled to the access device, said output generated by the input, the input and the output capacitively coupled to prevent the input disturbance from an output probe.

13. The device of claim 12, wherein the isolation circuit comprises one of:

buffer circuit, voltage modulation circuit, capacitor circuit, floating-gate circuit, inverter circuit, transistor circuit, thin-film transistor circuit, diode circuit and thin-film diode circuit.

14. The device of claim 12, wherein the output is coupled to a programmable logic element to program the logic element by altering the data state in the latch.

15. The device of claim 11, comprising a second access device coupled to the latch and further coupled to a second evaluation circuit, wherein the latch data can be altered by a second evaluation circuit bias condition.

16. The device of claim 11, wherein the latch comprises a volatile or non volatile memory element.

17. The device of claim 16, wherein the memory element is selected from a group of:

fuse links, latches, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, resistance modulating elements, optical elements, charge storage element, Carbon nano-tubes, voltage modulating element, and ferro-electric elements.

18. The device of claim 14, wherein the logic element comprises one or more of:

pass gate logic, multiplexer logic, truth table logic, look up table logic, AND logic, NAND logic OR logic, NOR logic, arithmetic logic, carry logic, floating point logic, and any other logic.

19. A semiconductor storage device, comprising:

a first port to write data to a storage element at ground or first voltage levels; and

a second port to read a signal at ground or second voltage levels generated by the storage element, wherein reading the generated signal protects data stored by the storage element from a read condition disturbance, and wherein the second voltage level is lower than the first voltage level.

20. The device of claim 19, the signal generated by the storage element is coupled to a programmable logic element to configure the programmable logic element.