Television functionality on a chip

• US 7,489,362 B2
• Filed: 03/03/2004
• Issued: 02/10/2009
• Est. Priority Date: 03/04/2003
• Status: Active Grant

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kranawetter, Greg A., Johnson, Shawn V., Bauch, Jeffrey S., Mamidwar, Rajesh, Chen, Iue-Shuenn, Law, Patrick, Cheung, Francis, Nhu, Hoang, Neuman, Darren D., Simon, Dan, Demas, Jason, Tang, Chengfuh Jeffrey, Bhatia, Sandeep, Delanghe, Brad, Baer, David A., Tran, Sang Van, Sweet, James D., Denk, Tracy C., Grossman, Brad, Shih, Guang-Ting, Schoner, Brian F., Nguyen, Ut, Monahan, Chuck, Nguyen, Thu T., Tingley, Jeff, Giese, Ben, Tseng, Hsien-Chih Jim, Tseng, Yao-Hua Steven, Movshovich, Aleksandr, Wu, David Chao Hua, Jaffe, Steven T., Ramakrishnan, Lakshman, Klingler, Keith LaRell
• Primary Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US10/791,686
• Publication Number:
  US 20050028220A1
• Time in Patent Office: 1,805 Days
• Field of Search: 348552-554, 348/725, 348/726, 348/731, 348/589, 348/600, 725/67, 725/68, 725/85, 725/100, 725/131, 725/139, 725/151
• US Class Current: 348/554
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/035 Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Abstract

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Claims

1. An integrated circuit for providing television functionality, comprising:

a plurality of input elements;

video and graphics processing elements;

audio processing elements, comprising;

an audio decoder including a signal mode detection system, wherein said signal mode detection system determines a transmission mode of a broadcast signal; and

an audio processor;

output interfaces; and

a control element, wherein said plurality of input elements, said video and graphics processing elements, said audio processing elements, and said output interfaces are coupled through a system controller.

2. The integrated circuit of claim 1, wherein said plurality of input elements comprise:

an IF demodulator; and

a data transport module.

3. The integrated circuit of claim 2, wherein said IF demodulator comprises a digital IF demodulator.

4. The integrated circuit of claim 2, wherein said IF demodulator includes an FM demodulation system for approximating y(n)=1/x(n) in FM demodulation, where x(n)=I²(n)+Q²(n).

5. The integrated circuit of claim 2, wherein said data transport module includes a video data stream front end processor.

6. The integrated circuit of claim 2, wherein said data transport module includes a packet substitution module.

7. The integrated circuit of claim 2, wherein said data transport module includes a media processing system.

8. The integrated circuit of claim 1, wherein said video and graphics processing elements comprise:

an analog video decoder;

a digital video decoder;

a video and graphics processing module coupled to said analog video decoder and said digital video decoder; and

a video encoder coupled to said video and graphics processing module.

9. The integrated circuit of claim 8, wherein said analog video decoder includes a 2D adaptive comb filter.

10. The integrated circuit of claim 8, wherein said digital video decoder includes an artificial time stamp module that generates pseudo MPEG information from received DV25 or DV50 digital video information.

11. The integrated circuit of claim 8, wherein said digital video decoder includes a 2D adaptive comb filter.

12. The integrated circuit of claim 8, wherein said video and graphics processing elements further comprise a 2D engine.

13. The integrated circuit of claim 8, wherein said video and graphics processing elements further comprise a 3D engine.

14. The integrated circuit of claim 8, wherein said video and graphics processing elements further comprise a combined color look-up and gamma correction system.

15. The integrated circuit of claim 8, wherein said video encoder includes a timing generator.

16. The integrated circuit of claim 8, wherein said digital video decoder includes a teletext decoder system.

17. The integrated circuit of claim 8, wherein said video encoder includes a MPAA HDTV copy protection filter system.

18. The integrated circuit of claim 1, further comprising an audio decoder digital interface coupled between an IF demodulator and said audio decoder, wherein said audio decoder digital interface provides an all digital interface and reduces signal mismatch.

19. The integrated circuit of claim 1, wherein the broadcast signal is a Japanese Broadcast Television System Committee broadcast signal.

20. The integrated circuit of claim 1, wherein said audio decoder includes a JBTSC signal separation processor configured to receive JBTSC signals and configured to process a main channel, a sub channel and a control channel of the JBTSC signals.

21. The integrated circuit of claim 1, wherein said audio decoder includes a digital signal processor (DSP) decoder having an execution unit, an address generator and an instruction set to decode input signals, wherein said digital signal processor decoder is reprogrammable and updateable.

22. The integrated circuit of claim 1, wherein said output interfaces includes one or more of:

an S-Video composite interface;

a 656 interface;

a RE modulation interface;

a digital audio port; and

an analog audio port.

23. The integrated circuit of claim 1, further comprising control interfaces.

24. The integrated circuit of claim 23, wherein said control interfaces include one or more of:

a DDR-DRAM controller;

an EJTAG module;

peripheral interfaces; and

an EBI interface.

25. The integrated circuit of claim 1, further comprising ancillary interfaces.

26. The integrated circuit of claim 25, wherein said ancillary interfaces include one or more of:

a USB 2.0 interface;

an Ethernet interface;

a V0.90 interface; and

a SATA interface.

27. The integrated circuit of claim 1, further comprising a reset synchronization system.

28. The integrated circuit of claim 1, further comprising an I/O multiplexing system.

29. The integrated circuit of claim 1, further comprising an adaptable strapping system.

30. The integrated circuit of claim 1, further comprising a multi-channel audio interconnect system.

31. An integrated circuit, comprising:

a digital IF demodulator for receiving and demodulating analog television signals;

an FM demodulation system for approximating y(n)=1/x(n) in FM demodulation, where x(n)=I²(n)+Q²(n);

a video data stream front end processor for demultiplexing video signals that use both a program identifier and are multiplexed using a time division multiplexing approach;

a packet substitution module for substituting packets into a video data stream;

a media processing system for processing multiple program channels containing one or more data packets;

a 2D adaptive comb filter for separating luma and chroma signals within a composite video signal;

an artificial time stamp module that generates pseudo MPEG information from received DV25 or DV50 digital video information;

a 2D engine that provides two dimensional graphics processing;

a 3D engine that provides three dimensional graphics processing;

a combined color look-up and gamma correction system that improves video graphics;

a timing generator for generating time-dependent control signals for video signals;

a teletext decoder system for processing teletext sequences;

a MPAA HDTV copy protection filter system for providing MPAA HDTV copy protection;

an audio decoder digital interface coupled between a IF demodulator and an audio decoder the provides and all digital interface and reduces signal mismatch;

signal mode detection system that determine a transmission mode of a broadcast signal; and

a digital signal processor within an audio decoder, wherein said digital signal processor is reprogrammable and updateable.

32. An integrated circuit for providing television functionality, comprising:

a plurality of input elements;

video and graphics processing elements, comprising

an analog video decoder;

a digital video decoder comprising an artificial time stamp module that generates pseudo MPEG information from received DV25 or DV50 digital video information;

a video and graphics processing module coupled to said analog video decoder and said digital video decoder; and

a video encoder coupled to said video and graphics processing module;

audio processing elements;

output interfaces; and

a control element, wherein said plurality of input elements, said video and graphics processing elements, said audio processing elements, and said output interfaces are coupled through a system controller.