Control circuit having frequency modulation to reduce EMI of power converters

• US 7,489,529 B2
• Filed: 11/08/2005
• Issued: 02/10/2009
• Est. Priority Date: 11/08/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Yang, Ta-yung
• Primary Examiner(s): Ullah; Akm E
• Assistant Examiner(s): Tran; Nguyen
• Application Number:
  US11/269,973
• Publication Number:
  US 20070103137A1
• Time in Patent Office: 1,190 Days
• Field of Search: 363/40, 363/39, 363/21.13, 363/21.17
• US Class Current: 363/40
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence

Abstract

A control circuit having frequency modulation is used for reducing the EMI of a power converter. A switching circuit is couple to a feedback circuit to generate a switching signal for regulating an output of the power converter. A first oscillator is equipped to determine a switching frequency of the switching signal. A second oscillator is coupled to the first oscillator to modulate the switching frequency of the switching signal for reduce the EMI of the power converter. A programmable resistor is designed to attenuate the feedback signal of the feedback circuit. The resistance of the programmable resistor is controlled by the output of the second oscillator. Therefore, the output power and the output voltage can be kept constant when the switching frequency is modulated.

Claims

1. A control circuit having frequency modulation, comprising:

a switching circuit, coupled to a feedback circuit to generate a switching signal for regulating an output of a power converter;

wherein said feedback circuit receives said output of said power converter for producing a feedback signal to control said switching signal;

a first oscillator, generating a clock signal to said switching circuit to determine a switching frequency of said switching signal;

a programmable capacitor, connected to said first oscillator for modulating a frequency of said clock signal;

a second oscillator, generating an oscillation signal, wherein an encoding circuit generates digital signals in response to said oscillation signal; and

a programmable resistor, coupled to said feedback circuit for attenuating said feedback signal;

wherein said digital signals control said programmable capacitor for modulating said switching frequency of said switching signal; and

said digital signals control said programmable resistor for programming an attenuation rate of said feedback signal.

2. The control circuit of claim 1, wherein said programmable capacitor comprises:

switching-capacitor couples, connected to each other in parallel, wherein said switching-capacitor couples are formed by couples of switches and capacitors connected in series respectively, wherein said switches are turned on/off by said digital signals.

3. The control circuit of claim 1, wherein said programmable resistor comprises:

switching-resistor couples, connected to each other in parallel, wherein said switching-resistor couples are formed by couples of attenuator switches and attenuator resistors connected in series respectively, wherein said attenuator switches are turned on/off by said digital signals.

4. The control circuit of claim 1, wherein said first oscillator comprises:

a charge-current source, for producing a charge current;

a discharge-current source, for producing a discharge current;

an osc capacitor, connected in parallel with said programmable capacitor;

an osc-charge switch, connected between said charge-current source and said osc capacitor;

an osc-discharge switch, connected between said discharge-current source and said osc capacitor;

a first comparator, wherein a first input of said first comparator is supplied with a first osc-threshold voltage, a second input of said first comparator being connected to said osc capacitor;

a second comparator, wherein a second input of said second comparator is supplied with a second osc-threshold voltage, a first input of said second comparator being connected to said osc capacitor, wherein said first osc-threshold voltage is higher than said second osc-threshold voltage;

a first gate, for producing said clock signal for determining said switching frequency of said switching signal, wherein a first input of said first gate is driven by an output of said first comparator, an output of said first gate turning on/off said osc-discharge switch; and

a second gate, wherein two inputs of said second gate are respectively connected to said output of said first gate and an output of said second comparator, wherein an output of said second gate is connected to a second input of said first gate, said output of said second gate turning on/off said osc-charge switch.

5. The control circuit of claim 1, wherein said encoding circuit comprises:

a plurality of comparators, having positive inputs supplied with said oscillation signal;

wherein negative inputs of said comparators are supplied with a plurality of threshold voltages respectively;

a plurality of flip-flops, having inputs coupled to outputs of said comparators respectively;

wherein clock inputs of said flip-flops are supplied with said clock signal; and

an encoder, coupled to outputs of said flip-flops for generating said digital signals.

6. A control circuit having frequency modulation, comprising:

a switching circuit, coupled to a feedback circuit to generate a switching signal for regulating an output of a power converter;

wherein said feedback circuit receives said output of said power converter for producing a feedback signal to control said switching signal;

a first oscillator, coupled to said switching circuit to determine a switching frequency of said switching signal;

a programmable capacitor, coupled to said first oscillator to modulate said switching frequency of said switching signal;

a second oscillator, generating an oscillation signal, wherein an analog-to-digital converter generates digital signals in response to said oscillation signal; and

a programmable resistor, coupled to said feedback circuit for attenuating said feedback signal;

wherein said digital signals are coupled to control a capacitance of said programmable capacitor and a resistance of said programmable resistor.

7. The control circuit of claim 6, wherein said programmable capacitor comprises:

switching-capacitor couples, connected to each other in parallel, wherein said switching-capacitor couples are formed by couples of switches and capacitors connected in series respectively, wherein said switches are turned on/off by said digital signals.

8. The control circuit of claim 6, wherein said programmable resistor comprises:

switching-resistor couples, connected to each other in parallel, wherein said switching-resistor couples are formed by couples of attenuator switches and attenuator resistors connected in series respectively, wherein said attenuator switches are turned on/off by said digital signals.

9. The control circuit of claim 6, wherein said first oscillator comprises:

a charge-current source, for producing a charge current;

a discharge-current source, for producing a discharge current;

an osc capacitor, connected in parallel with said programmable capacitor;

an osc-charge switch, connected between said charge-current source and said osc capacitor;

an osc-discharge switch, connected between said discharge-current source and said osc capacitor;

a first comparator, wherein a first input of said first comparator is supplied with an first osc-threshold voltage, a second input of said first comparator being connected to said osc capacitor;

a second comparator, wherein a second input of said second comparator is supplied with a second osc-threshold voltage, a first input of said second comparator is connected to said osc capacitor, wherein said first osc-threshold voltage is higher than said second osc-threshold voltage;

a first gate, coupled to said switching circuit for determining said switching frequency of said switching signal, wherein a first input of said first gate is driven by an output of said first comparator, wherein an output of said first gate turns on/off said osc-discharge switch; and

a second gate, wherein two inputs of said second gate are respectively connected to said output of said first gate and an output of said second comparator, wherein an output of said second gate is connected to a second input of said first gate, wherein said output of said second gate turns on/off said osc-charge switch.

10. The control circuit of claim 6, wherein said analog-to-digital converter comprises:

a plurality of comparators, having positive inputs supplied with said oscillation signal;

wherein negative inputs of said comparators are supplied with a plurality of threshold voltages respectively;

a plurality of flip-flops, having inputs coupled to outputs of said comparators respectively;

wherein clock inputs of said flip-flops are coupled to an output of said first oscillator; and

an encoder, coupled to outputs of said flip-flops for generating said digital signals.