Hardware implementation of the secure hash standard

• US 7,489,779 B2
• Filed: 03/05/2002
• Issued: 02/10/2009
• Est. Priority Date: 03/22/2001
• Status: Expired due to Term

• Current Assignee: QST Holdings LLC
• Original Assignee: QST Holdings LLC
• Inventors: Scheuermann, Walter James
• Primary Examiner(s): Simitoski, Michael J
• Application Number:
  US10/093,156
• Publication Number:
  US 20030135743A1
• Time in Patent Office: 2,534 Days
• Field of Search: 380/28, 713/161, 713/164, 713/201, 713/16, 703/2, 712/15, 712/29, 712/37, 716/16
• US Class Current: 380/28
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.

Claims

1. An integrated circuit for implementing a secure hash algorithm, comprising:

a data path configured to process an input message by performing rounds of the secure hash algorithm, the data path comprising hardware components that are reconfigurable; and

a controller configured to control operation of the data path in performing the rounds of the secure hash algorithm, the controller comprising hardware components including an address control module and a finite state machine that cooperate with each other to provide control bits and physical memory addresses during each round of the secure hash algorithm;

wherein at least some of the hardware components of the data path are reconfigured during each round of the secure hash algorithm in response to the control bits provided during each round of the secure hash algorithm; and

wherein variable values stored in a variable memory are provided to the data path for processing during each round of the secure hash algorithm in response to the physical memory addresses provided during each round of the secure hash algorithm.

2. The integrated circuit of claim 1 wherein the control bits and the physical memory addresses are provided during each round of the secure hash algorithm to enable the data path to perform reiterative processing of each round of the secure hash algorithm.

3. The integrated circuit of claim 1 wherein the address control module includes:

a code memory configured to store codes that are used to direct performance of each round of the secure hash algorithm, the codes comprising the control bits provided during each round of the secure hash algorithm and address information for generating the physical memory addresses provided during each round of the secure hash algorithm.

4. The integrated circuit of claim 3 wherein the variables include longwords, intermediate variables, initialization constants, and processing constants.

5. The integrated circuit of claim 3 wherein the address control module further includes:

a modulo counter configured to fetch the codes in the code memory that are used to direct performance of each round of the secure hash algorithm; and

an address generator configured to generate the physical memory addresses based on the address information in the codes that are used to direct performance of each round of the secure hash algorithm.

6. The integrated circuit of claim 5 wherein:

the finite state machine provides state information regarding the state of the implementation of the secure hash algorithm; and

the address generator generates the physical memory addresses during each round of the secure hash algorithm further based upon the state information provided by the finite state machine.

7. The integrated circuit of claim 1 wherein:

the finite state machine provides state information regarding the state of the secure hash algorithm; and

the address control module provides the control bits and the physical memory addresses during each round of the secure hash algorithm based upon the state information provided by the finite state machine.

8. The integrated circuit of claim 1 wherein the integrated circuit further comprises the variable memory.

9. A network communication device having the integrated circuit of claim 1.

10. An integrated circuit for implementing a secure hash algorithm with multiple rounds, comprising:

a data path circuit comprising the following hardware components;

a variable memory;

a first multiplexor coupled to the variable memory;

a first register coupled to the first multiplexor;

a shifter coupled to the first register;

an arithmetic logic unit coupled to the shifter and the first multiplexor;

a second register coupled to the arithmetic logic unit; and

a second multiplexor coupled to the second register, the variable memory and the arithmetic logic unit; and

a controller configured to control operation of the data path circuit, comprising;

a finite state machine; and

an address control module operable in conjunction with the finite state machine to generate physical memory addresses and control bits during each round of the secure hash algorithm;

wherein at least some of the hardware components of the data path circuit are reconfigurable and are reconfigured during each round of the secure hash algorithm in response to the control bits provided during each round of the secure hash algorithm; and

wherein the variable memory provides variable values during each round of the secure hash algorithm for processing by others of the hardware components of the data path circuit in response to the physical memory addresses provided during each round of the secure hash algorithm.

11. The integrated circuit of claim 10 wherein the address control module further includes:

a code memory configured to store codes that are used to direct performance of each round of the secure hash algorithm, the codes comprising the control bits provided during each round of the secure hash algorithm and address information for generating the physical memory addresses provided during each round of the secure hash algorithm.

12. The integrated circuit of claim 11 wherein the address control module further includes:

a modulo counter configured to fetch the codes in the code memory that are used to direct performance of each round of the secure hash algorithm; and

an address generator configured to generate the physical memory addresses based on the address information in the codes that are used to direct performance of each round of the secure hash algorithm.

13. The integrated circuit of claim 12 wherein:

the finite state machine provides state information regarding the state of the implementation of the secure hash algorithm; and

the address generator generates the physical memory addresses during each round of the secure hash algorithm further based upon the state information provided by the finite state machine.

14. The integrated circuit of claim 10 wherein the variables include longwords, intermediate variables, initialization constants, and processing constants.

15. A communication device having the integrated circuit of claim 10.

16. The integrated circuit of claim 10 wherein the control bits and the physical memory addresses are provided during each round of the secure hash algorithm to enable the data path circuit to perform reiterative processing of each round of the secure hash algorithm.

17. The integrated circuit of claim 10 wherein:

the finite state machine provides state information regarding the state of the secure hash algorithm; and

the address control module provides the control bits and the physical memory addresses during each round of the secure hash algorithm based upon the state information provided by the finite state machine.

18. A method of implementing multiple rounds of a secure hash algorithm, the method comprising:

configuring a reconfigurable hardware data path to process an input message by performing rounds of the secure hash algorithm, the data path comprising hardware components that are reconfigurable; and

configuring a reconfigurable hardware controller including a finite state machine to control operation of the data path during each round, and an address control module, the address control module and the finite state machine cooperating with each other to provide control bits and physical memory addresses during each round of the secure hash algorithm;

wherein at least some of the hardware components of the data path are reconfigured during each round of the secure hash algorithm in response to the control bits provided during each round of the secure hash algorithm; and

wherein variable values stored in a variable memory are provided to the data path for processing during each round of the secure hash algorithm in response to the physical memory addresses provided during each round of the secure hash algorithm.

19. The method of claim 18, wherein the control bits and the physical memory addresses are provided during each round of the secure hash algorithm to enable the data path to perform reiterative processing of each round of the secure hash algorithm.

20. The method of claim 18, wherein the address control module includes:

a code memory configured to store of codes that are used to direct performance of each round of the secure hash algorithm, the codes comprising the control bits provided during each round of the secure hash algorithm and address information for generating the physical memory addresses provided during each round of the secure hash algorithm.

21. The method of claim 18, wherein the variables include longwords, intermediate variables, initialization constants, and processing constants.