Fully buffered DIMM system and method with hard-IP memory controller and soft-IP frequency controller
First Claim
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1. A system for memory control, the system comprising:
- a hard-IP memory controller;
a soft-IP frequency conversion system coupled to the hard-IP memory controller;
an interface system coupled to at least the soft-IP frequency conversion system;
wherein the interface system includes a physical media attachment electrical interface and a physical coding sub-layer;
wherein the soft-IP frequency conversion system is capable of being programmed to convert data signals between a first frequency and a second frequency;
wherein the hard-IP memory controller includes a first plurality of devices associated with cyclic redundancy check and a second plurality of devices associated with error correction code.
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Abstract
A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is coupled to the hard-IP memory controller, and is capable of being programmed to convert data signals between a first frequency and a second frequency.
36 Citations
26 Claims
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1. A system for memory control, the system comprising:
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a hard-IP memory controller; a soft-IP frequency conversion system coupled to the hard-IP memory controller; an interface system coupled to at least the soft-IP frequency conversion system; wherein the interface system includes a physical media attachment electrical interface and a physical coding sub-layer; wherein the soft-IP frequency conversion system is capable of being programmed to convert data signals between a first frequency and a second frequency; wherein the hard-IP memory controller includes a first plurality of devices associated with cyclic redundancy check and a second plurality of devices associated with error correction code. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A system for memory control, the system comprising:
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a hard-IP memory controller; a soft-IP frequency conversion system coupled to the hard-IP memory controller; an interface system coupled to at least the soft-IP frequency conversion system; wherein the interface system includes a physical media attachment electrical interface and a physical coding sub-layer; wherein the hard-IP memory controller is capable of providing first instructions to the interface system, receiving first data from the interface system, and sending second data to the interface system; wherein the soft-IP frequency conversion system is capable of being programmed to convert data signals between a first frequency and a second frequency, the first frequency being anyone of a plurality of frequencies. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A system for memory control, the system comprising:
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a hard-IP memory controller; a soft-IP frequency conversion system coupled to the hard-IP memory controller; an interface system coupled to at least the soft-IP frequency conversion system; wherein the interface system is capable of transmitting first data to a memory buffer and receiving second data from the memory buffer; wherein the hard-IP memory controller is capable of providing instructions to the interface system, sending the first data to the interface system, and receiving the second data from the interface system; wherein the soft-IP frequency conversion system is capable of being programmed to convert data signals between a first frequency and a second frequency. - View Dependent Claims (24, 25, 26)
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Specification