Memory hub with integrated non-volatile memory

• US 7,490,211 B2
• Filed: 05/03/2006
• Issued: 02/10/2009
• Est. Priority Date: 09/18/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Schnepper, Randy L.
• Primary Examiner(s): Portka; Gary J
• Application Number:
  US11/417,751
• Publication Number:
  US 20060200620A1
• Time in Patent Office: 1,014 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory controller includes registers into which the memory configuration information is loaded and is operable to output memory requests in response to receiving memory access requests from the high-speed interface and in accordance with the memory configuration information loaded in the registers. A method for initializing a memory sub-system is also provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub.

Claims

1. A memory hub in a hub-based memory sub-system, comprising:

a non-volatile memory for storing memory module configuration information that is stored in the non-volatile memory before initialization and specific to a memory module on which the memory hub is located;

a first configuration path coupled to the non-volatile memory and configured to provide access to the non-volatile memory; and

a memory controller coupled to the non-volatile memory through the first configuration path and further coupled to a plurality of memory devices of the memory module, the memory controller having a plurality of configuration registers configured by loading the memory module configuration information from the non-volatile memory, the memory controller operable to output memory requests to the plurality of memory devices in response to receiving memory access requests and in accordance with the memory module configuration information loaded in the plurality of registers;

a link interface coupled to the memory controller, the link interface configured to receive memory access requests from a host system; and

a second configuration path coupled to the link interface and the non-volatile memory, the second configuration path configured to provide the link interface access to the non-volatile memory.

2. The memory hub of claim 1, further comprising a local serial bus coupled to the non-volatile memory and configured to provide a host system access to the non-volatile memory.

3. The memory hub of claim 1 wherein the non-volatile memory comprises an embedded non-volatile memory integrated with the memory controller.

4. The memory hub of claim 3 wherein the embedded non-volatile memory comprises an embedded array of electrically erasable programmable read-only memory.

5. The memory hub of claim 1 wherein the memory controller is coupled to a plurality of memory devices through a memory device bus, the memory controller configured to provide and receive signals specific to the plurality of memory devices coupled to the memory controller.

6. The memory hub of claim 1 wherein the memory controller is coupled to a plurality of memory devices through a memory device bus, the memory controller capable of operating with the plurality of memory devices that operate at different clock frequencies.

7. The memory hub of claim 1 wherein the memory module configuration information comprises at least one of timing information for a plurality of memory devices coupled to the memory controller of the memory module, memory module configuration data, memory device type, and manufacturer data.

8. The memory hub of claim 1 wherein the memory module configuration information comprises module specific information used by a host system comprising at least one of memory module capacity and memory module clock speed.

9. A memory sub-system for a host system, comprising:

a bus coupled to the host system; and

at least one memory module, each memory module having a plurality of memory devices and further having a memory hub, the memory hub coupled to the bus and the plurality of memory devices to control access to the memory devices, the memory hub including a memory controller coupled to the plurality of memory devices of the memory module to output memory access requests to the plurality of memory devices, the memory hub further including a non-volatile memory for storing memory module configuration information that is stored in the non-volatile memory before initialization and specific to the memory module, the non-volatile memory being coupled to the memory controller through a first configuration path to provide the memory controller with the memory module configuration information;

a link interface coupled to the memory controller, the link interface configured to receive memory access requests from the host system; and

a second configuration path coupled to the link interface and the non-volatile memory, the second configuration path configured to provide the link interface access to the non-volatile memory.

10. The memory sub-system of claim 9, further comprising a local serial bus coupled to the non-volatile memory and configured to provide the host system access to the non-volatile memory.

11. The memory sub-system of claim 9 wherein the non-volatile memory comprises an embedded non-volatile memory integrated with the memory controller.

12. The memory sub-system of claim 11 wherein the embedded non-volatile memory comprises an embedded array of electrically erasable programmable read-only memory.

13. The memory sub-system of claim 9 wherein the memory controller comprises a memory controller configured to provide and receive signals specific to the plurality of memory devices coupled to the memory controller.

14. The memory sub-system of claim 9 wherein the memory controller comprises a memory controller capable of operating with the plurality of memory devices that operate at different clock frequencies.

15. The memory sub-system of claim 9 wherein the memory module configuration information comprises at least one of timing information for a plurality of memory devices coupled to the memory controller of the memory module, memory module configuration data, memory device type, and manufacturer data.

16. The memory sub-system of claim 9 wherein the memory module configuration information comprises module specific information used by the host system comprising at least one of memory module capacity and memory module clock speed.

17. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the plurality of memory devices, the memory hub having a non-volatile memory for storing memory module configuration information that is stored in the non-volatile memory before initialization and specific to the memory module, the memory hub further having a memory controller coupled to the plurality of memory devices, the memory controller coupled to the non-volatile memory through a first configuration path, the memory controller operable to output memory requests to the plurality of memory devices in response to receiving memory access requests and in accordance with the memory module configuration information stored in the non-volatile memory;

a link interface coupled to the memory controller, the link interface configured to receive memory access requests from a host system; and

a second configuration path coupled to the link interface and the non-volatile memory, the second configuration path configured to provide the link interface access to the non-volatile memory.

18. The memory module of claim 17, further comprising a local serial bus coupled to the non-volatile memory and configured to provide a host system access to the non-volatile memory.

19. The memory module of claim 17 wherein the non-volatile memory comprises an embedded non-volatile memory integrated with the memory controller.

20. The memory module of claim 19 wherein the embedded non-volatile memory comprises an embedded array of electrically erasable programmable read-only memory.

21. The memory module of claim 17 wherein the memory controller comprises a memory controller configured to provide and receive signals specific to the plurality of memory devices coupled to the memory controller.

22. The memory module of claim 17 wherein the memory controller comprises a memory controller capable of operating with the plurality of memory devices that operate at different clock frequencies.

23. The memory module of claim 17 wherein the memory module configuration information comprises at least one of timing information for a plurality of memory devices coupled to the memory controller of the memory module, memory module configuration data, memory device type, and manufacturer data.

24. The memory module of claim 17 wherein the memory module configuration information comprises module specific information used by a host system comprising at least one of memory module capacity and memory module clock speed.

25. A method of initializing a memory sub-system, comprising:

accessing a non-volatile memory that stores configuration information specific to the memory sub-system on which a memory hub having the non-volatile memory is located, the configuration information being stored in the non-volatile memory before initialization;

loading a configuration register of the memory hub with the configuration information from the non-volatile memory through a first configuration path;

receiving memory access requests from a host system through a link interface; and

providing the link interface access to the non-volatile memory through a second configuration path.

26. The method of claim 25, further comprising providing the configuration information from the non-volatile memory to a register of a system memory controller to which the non-volatile memory is coupled.

27. The method of claim 26 wherein providing the configuration information to the register of the system memory controller comprises coupling the configuration information to a serial bus to which the system memory controller is coupled.

28. The method of claim 26 wherein providing the configuration information to the register of the system memory controller comprises providing at least one of memory module capacity and memory module clock speed.

29. The method of claim 25 wherein accessing the non-volatile memory comprises accessing an electrically erasable programmable read-only memory.

30. The method of claim 25 wherein accessing the non-volatile memory comprises accessing an embedded non-volatile memory.

31. The method of claim 25 wherein loading the configuration register of the memory hub with the configuration information comprises loading at least one of timing information for a plurality of memory devices of a memory module, memory module configuration data, memory device type, and manufacturer data.