Method for driving values to DC adjusted/untimed nets to identify timing problems

• US 7,490,305 B2
• Filed: 07/17/2006
• Issued: 02/10/2009
• Est. Priority Date: 07/17/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ja, Yee, Gass, Robert B., Jaeschke, Christoph
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Doan; Nghia M
• Application Number:
  US11/457,865
• Publication Number:
  US 20080016480A1
• Time in Patent Office: 939 Days
• Field of Search: 716 4- 6
• US Class Current: 716/136
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method for driving values to “don'"'"'t care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Claims

1. A method, in a data processing device, for verifying an operation of untimed net segments of an integrated circuit design, comprising:

receiving the integrated circuit design;

receiving a “

don'"'"'t care”

(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;

comparing entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;

driving a value along a pathway to the at least one untimed net segment;

monitoring an output state value from the untimed net segment;

verifying an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;

determining whether there is a violation in the operation of the untimed net segment;

determining whether downstream logic in the integrated circuit design uses the output value; and

removing the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.

2. The method of claim 1, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

3. The method of claim 1, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

4. The method of claim 3, further comprising:

outputting a result of the verification, wherein the result identifies untimed net segments that are not verified as maintaining the predetermined value.

5. The method of claim 1, further comprising:

replicating, in the integrated circuit design, a pathway to the untimed net segment, wherein driving the value along a pathway to the at least one untimed net segment comprises driving the value along the replicated pathway to the untimed net segment.

6. The method of claim 1, wherein driving a value along a pathway to the at least one untimed net segment comprises:

driving one of an indeterminate value or a random value along the pathway to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

7. The method of claim 6, wherein the verification analysis uses a logical built-in self test mode of operation of the integrated circuit device.

8. The method of claim 1, wherein an indeterminate value is driven along the pathway to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

9. The method of claim 1, further comprising:

responsive to there being a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design using the output value, notifying a designer that the untimed net segment has a timing error.

10. The method of claim 9, further comprising:

responsive to there being a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design using the output value, notifying a designer that the untimed net segment has a timing error.

11. A method, in a data processing device, for verifying an operation of untimed net segments of an integrated circuit design, comprising:

receiving the integrated circuit design;

receiving a “

don'"'"'t care”

(DC) adjusted list that identifies net segments that do not need to adhere to timing requirements;

comparing entries in the DC adjusted list to a netlist for the integrated circuit design to identify an untimed net segment based on a match of a net segment in the DC adjusted list with a net in the netlist for the integrated circuit design;

converting the untimed net segment to single source and single sink net;

identifying a source latch that feeds the untimed net segment;

identifying, in the integrated circuit design, a path to the untimed net segment from its source latch;

replicating, in the integrated circuit design, the identified path to form a replicated path;

driving a value to the untimed net segment along the identified path and the replicated path;

monitoring an output state value from the untimed net segment; and

verifying an operation of the untimed net segment of the integrated circuit design based on the collected output value from the untimed net segment;

determining whether there is a violation in the operation of the untimed net segment;

determining whether downstream logic in the integrated circuit design uses the output value; and

removing the untimed net segment from the DC adjusted list if there is a violation in the operation of the untimed net segment and downstream logic in the integrated circuit design does not use the output value.

12. The method of claim 11, wherein the operation of the untimed net segment is verified if the output value from the untimed net segment maintains a predetermined value.

13. The method of claim 11, wherein the operation of the untimed net segment is not verified if the output value from the untimed net segment achieves a value different from a predetermined value.

14. The method of claim 13, further comprising:

outputting a result of the verification, wherein the result identifies untimed net segments that are not verified as maintaining the predetermined value.

15. The method of claim 11, wherein driving a value to the at least one untimed net segment comprises:

driving one of an indeterminate value or a random value to the at least one untimed net segment; and

performing one of formal, semi-formal, or non-formal verification analysis on the integrated circuit design using the driven value.

16. The method of claim 15, wherein the verification analysis uses a logical built-in self test mode of operation of the integrated circuit device.

17. The method of claim 11, wherein an indeterminate value is driven to the at least one untimed net segment, and wherein if the collected output value from the untimed net is an indeterminate value, the untimed net segment is determined to be invalid.

18. The method of claim 11, wherein converting the untimed net segment to single source and single sink net comprises inserting at least one transparent latch into the integrated circuit design.