Method and apparatus for controlling a circuit with a high voltage sense device

• US 7,491,611 B2
• Filed: 03/09/2007
• Issued: 02/17/2009
• Est. Priority Date: 07/08/2004
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald R.
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US11/716,057
• Publication Number:
  US 20070155062A1
• Time in Patent Office: 711 Days
• Field of Search: 257339-343, 257/409, 327533-534, 438/157, 438/282
• US Class Current: 438/282
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

Claims

1. A method of fabricating a voltage sense device, comprising:

forming a first doped region in a well included in a substrate;

forming a second doped region in the substrate outside of the well;

forming a third doped region in the well;

coupling a first terminal to the well via the first doped region;

coupling a second terminal to the substrate via the second doped region; and

coupling a third terminal to the well via the third doped region, wherein a voltage output by the voltage sense device at the third terminal is substantially proportional to a voltage between the first and second terminals when the voltage between the first and second terminals is less than a pinch-off voltage of the voltage sense device, wherein the voltage output by the voltage sense device at the third terminal is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch-off voltage of the voltage sense device.

2. The method of fabricating the voltage sense device of claim 1, further comprising forming an oxide layer on a top portion of the well between the first and third doped regions.

3. The method of fabricating the voltage sense device of claim 2, wherein the oxide layer comprises a first and a second oxide layer, the method further comprising forming a field plate between the first and second oxide layers proximate to a region between the first terminal and the well.

4. The method of fabricating the voltage sense device of claim 3, further comprising forming a p-type region on a surface of the n-well extending across a portion of the n-well between the first and third n-doped regions.

5. The method of fabricating the voltage sense device of claim 1, wherein the substrate comprises a p-type substrate, the well comprises an n-well, the first doped region comprises a first n-doped region, the second doped region comprises a second p-doped region, and the third doped region comprises a third n-doped region.

6. The method of fabricating the voltage sense device of claim 5, further comprising embedding at least one p-doped region within the n-well extending across a portion of the n-well between the first and third n-doped regions.

7. The method of fabricating the voltage sense device of claim 6, wherein the at least one p-type region embedded within the n-well is electrically coupled to the p-type substrate.

8. The method of fabricating the voltage sense device of claim 1, further comprising electrically coupling the second terminal to a ground reference voltage of the substrate.

9. A voltage sense device, comprising:

a substrate including a well formed in the substrate;

a first doped region disposed in the well;

a second doped region disposed in the substrate outside of the well;

a third doped region disposed in the well;

a first terminal coupled to the well via the first doped region;

a second terminal coupled to the substrate via the second doped region; and

a third terminal coupled to the well via the third doped region, wherein a voltage output by the voltage sense device at the third terminal is substantially proportional to a voltage between the first and second terminals when the voltage between the first and second terminals is less than a pinch-off voltage of the voltage sense device, wherein the voltage output by the voltage sense device at the third terminal is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch-off voltage of the voltage sense device.

10. The voltage sense device of claim 9, further comprising an oxide layer disposed on a surface of the well between the first and third doped regions.

11. The voltage sense device of claim 10, wherein the oxide layer comprises a first and a second oxide layer, the voltage sense device further comprising a field plate disposed between the first and second oxide layers proximate to a region between the first terminal and the well.

12. The voltage sense device of claim 9, wherein the substrate comprises a p-type substrate, the well comprises an n-well, the first doped region comprises a first n-doped region, the second doped region comprises a second p-doped region, and the third doped region comprises a third n-doped region.

13. The voltage sense device of claim 12, further comprising at least one p-doped region embedded within the n-well extending across a portion of the n-well between the first and third n-doped regions.

14. The voltage sense device of claim 13, wherein the at least one p-type region embedded within the n-well is electrically coupled to the p-type substrate.

15. The voltage sense device of claim 12, further comprising a p-type region disposed on a surface of the n-well extending across a portion of the n-well between the first and third n-doped regions.

16. The voltage sense device of claim 9, wherein the second terminal is electrically coupled to a ground reference voltage of the substrate.