Method of making a semiconductor structure

• US 7,491,623 B2
• Filed: 08/20/2007
• Issued: 02/17/2009
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Byeong Y., Nayfeh, Hasan M., Chen, Xiaomeng, Jeng, Shwu-Jen
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Swanson; Walter H.
• Application Number:
  US11/841,018
• Publication Number:
  US 20080057673A1
• Time in Patent Office: 547 Days
• Field of Search: 438/439, 257/E21.54
• US Class Current: 438/439
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

Claims

1. A method for manufacturing a device, comprising:

forming a layer on a substrate;

forming a gate on the layer;

forming an undercut under the gate by removing portions of the layer;

forming a barrier layer within the undercut completely filling the undercut to protect the layer from corrosion during subsequent processing steps; and

processing source and drain regions,

wherein the layer is an oxide layer, and

the barrier layer forms sidewalls abutting the gate which are of thickness of less than 10 nm.

2. The method according to claim 1, further comprising removing the barrier layer after processing of the source and drain regions.

3. The method according to claim 1, wherein the processing includes a pre-cleaning prior to filling the source and drain regions with material.

4. The method according to claim 1, wherein the processing of the source and drain regions includes forming wells beyond an edge of the undercut, below the gate.

5. The method according to claim 1, wherein the removing portions of the layer comprises hydrofluoric acid etching.

6. The method according to claim 1, wherein the processing of the source and drain regions includes isotropic or anisotropic etching of source and drain wells.

7. The method according to claim 1, wherein the barrier layer electrically isolates the gate from the source and drain regions.

8. A method for forming a gate oxide seal, comprising:

forming a gate on a substrate including a gate oxide layer formed between the substrate and the gate;

etching portions of the gate oxide layer thereby forming an undercut under the gate;

protecting all exposed portions of the gate oxide layer while forming sidewalls abutting the gate;

etching source and drain wells into the substrate adjacent the gate; and

filling the source and drain wells with conductive material,

wherein the barrier layer forms sidewalls abutting the gate which are of a thickness of less than 10 nm.

9. The method according to claim 8, wherein the etching of source and drain wells comprises isotropic or anistropic etching and the protecting steps seals the gate oxide layer from the conductive material with portions of the non-conductive sidewalls.

10. The method according to claim 8, wherein the filling of the source and drain wells comprises epitaxially growing silicon germanium material.

11. A method of forming a structure, comprising:

forming a gate oxide layer on a substrate;

forming a gate on the gate oxide layer;

forming a material about walls of the gate and formed within an undercut underneath the gate, completely filling the undercut, to protect regions of the gate oxide layer exposed by the undercut; and

isolating source and drain regions from the gate by the material,

wherein the material about the walls of the gate is a thickness of less than 10 nm.

12. The method according to claim 11, wherein the gate oxide layer comprises high dielectric constant (high-k) material.

13. The method according to claim 11, wherein the source and drain regions are grown epitaxially from silicon germanium material.

14. The method according to claim 11, wherein the gate oxide layer has a thickness from about 0.5 nm to about 3 nm.

15. The method according to claim 11, wherein the material is a protective barrier layer of silicon nitride forming sidewalls.

16. The method according to claim 11, wherein the source and drain regions are formed under the gate, beyond at least a portion of the undercut.