Semiconductor device and manufacturing method of semiconductor device

• US 7,492,011 B2
• Filed: 11/15/2005
• Issued: 02/17/2009
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Teruo, Hashimoto, Kenji, Nomura, Toshio
• Primary Examiner(s): Nguyen; Dao H.
• Application Number:
  US11/273,400
• Publication Number:
  US 20060273398A1
• Time in Patent Office: 1,190 Days
• Field of Search: 257/173, 257/355, 257/360, 438/224, 438/309
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

Claims

1. A semiconductor device including ESD protective circuits for enhancing a tolerance to an electrostatic discharge breakdown, comprising:

a substrate of a first conductive type,

a first region forming a plurality of first ESD protective circuits in a finger structure, and

a second region forming a plurality of second ESD protective circuits in the finger structure,

wherein each of the first ESD protective circuits includes;

a first transistor having a first gate electrode, and a first drain electrode including a first diffusion region of a second conductive type, and

a first ballast resistance including a second diffusion region of the second conductive type connected to the first diffusion region in a direction apart from the first gate electrode, with an impurity concentration lower than the concentration of the first diffusion region, and

each of the second ESD protective circuits includes;

a second transistor having a second gate electrode, and a second drain electrode including a third diffusion region of the second conductive type, having dielectric strength of a gate oxide lower than that of the first transistor, and

a second ballast resistance including a fourth diffusion region of the second conductive type connected to the third diffusion region in a direction apart from the second gate electrode, with the impurity concentration higher than the concentration of the second diffusion region.

2. The semiconductor device of claim 1,

wherein the second ballast resistance includes a fifth diffusion region with the impurity concentration same as concentration of the second diffusion region.

3. The semiconductor device of claim 2,

wherein the fourth diffusion region is disposed in a direction apart from the surface of the substrate further than the fifth diffusion region.

4. The semiconductor device of claim 1,

wherein the second drain electrode of the second transistor has an LDD region, and

the second diffusion region has the impurity concentration same as or higher than the concentration of the LDD region.

5. A manufacturing method of the semiconductor device of claim 1, comprising:

a step of forming the fourth diffusion region by implanting a first impurity element of the second conductive type selectively in the second ballast resistance, and

a step of forming a second diffusion region by implanting a second impurity element of the second conductive type at least in the first ballast resistance after forming the fourth diffusion region.

6. The manufacturing method of semiconductor device of claim 5,

wherein the second drain electrode of the second transistor has the LDD region, and

the step of forming the second diffusion region serves also as a step of implanting the second impurity element of the second conductive type in the LDD region.

7. The manufacturing method of semiconductor device of claim 5,

wherein the step of forming the second diffusion region serves also as a step of implanting the second impurity element of the second conductive type also in the second ballast resistance.