Semiconductor device

• US 7,492,031 B2
• Filed: 05/16/2006
• Issued: 02/17/2009
• Est. Priority Date: 12/25/2003
• Status: Expired due to Fees

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiyama, Koichi, Ninomiya, Hideaki, Yamaguchi, Masakazu, Inoue, Tomoki
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US11/434,185
• Publication Number:
  US 20060202308A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/137, 257/138, 257/341, 257/526, 257/561, 257/563, 257/565
• US Class Current: 257/526
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

Claims

1. A semiconductor device comprising:

a first base layer of a first conductive type which has a first surface and a second surface;

a second base layer of a second conductive type which is formed on the first surface;

a source layer of a first conductive type which is formed on a surface region of the second base layer;

an emitter layer of the second conductive type which is formed on the second surface;

a first gate electrode which is formed on the second base layer via a gate insulating layer between the source layer and the first base layer;

a second gate electrode which is formed on the first base layer via a gate insulating layer and is formed at a site apart from the first gate electrode;

an emitter electrode which is formed on the second base layer and the source layer; and

a collector electrode which is formed on the emitter layer.

2. The semiconductor device according to claim 1 further comprising:

a controller controlling the first and second gate electrodes by inputting a turn-on signal or a turn-off signal to the first and second gate electrodes.

3. The semiconductor device according to claim 2, wherein

the controller controls to output the turn-on signal or the turn-off signal to the first and the second gate electrode at a same timing.

4. The semiconductor device according to claim 2, wherein

the controller controls to output the turn-off signal to the first gate electrode after outputting the turn-off signal to the second gate electrode.

5. The semiconductor device according to claim 2, wherein the controller controls to output the turn-on signal to the second gate electrode after outputting the turn-on signal to the first gate electrode.

6. The semiconductor device according to claim 1 further comprising:

a capacitor connected between the second gate electrode and the emitter electrode.

7. The semiconductor device according to claim 1 further comprising:

an insulating film formed on the first and second gate electrodes;

wherein the emitter electrode is formed on the first and second gate electrodes via the insulating film, and a thickness of the insulating film on the second gate electrode is smaller than that of the insulating film on the first gate electrode.

8. The semiconductor device according to claims 1, wherein the first and the second gate electrodes are electrically disconnected from each other.

9. The semiconductor device according to claim 8 further comprising:

first and a second terminals which are electrically connected to the first and the second gate electrodes, respectively, and the first and the second terminals are electrically disconnected from each other.

10. The semiconductor device according to claim 1 further comprising:

a terminal connected electrically to the first and the second gate electrodes.

11. The semiconductor device according to claim 10, wherein a capacitance between the first gate electrode and the emitter electrode is different from a capacitance between the second gate electrode and the emitter electrode.

12. The semiconductor device according to claim 1, wherein a turn-on voltage applied to the first gate electrode is different from a turn-on voltage applied to the second gate electrode, and a turn-off voltage applied to the first gate electrode is different from a turn-off voltage applied to the second gate electrode.

13. The semiconductor device according to claim 12, wherein the turn-on voltage applied to the second gate electrode is higher than the turn-on voltage applied to the first gate electrode, and an absolute value of the turn-off voltage applied to the second gate electrode is higher than an absolute value of a turn-off voltage applied to the first gate electrode.

14. The semiconductor device according to claim 12, wherein the turn-on voltage applied to the second gate electrode is higher than the turn-on voltage applied to the first gate electrode, or an absolute value of the turn-off voltage applied to the second gate electrode is higher than an absolute value of a turn-off voltage applied to the first gate electrode.

15. The semiconductor device according to claim 1, wherein one of the first gate electrodes is disposed between two of the second gate electrodes.

16. The semiconductor device according to claim 1, wherein one of the first gate electrodes and two of the second gate electrodes form a unit cell, and a plurality of the unit cells are arranged repeatedly.

17. The semiconductor device according to claim 1, wherein a turn-on voltage applied to the first gate electrode is different from a turn-on voltage applied to the second gate electrode, or a turn-off voltage applied to the first gate electrode is different from a turn-off voltage applied to the second gate electrode.