Interconnection and input/output resources for programmable logic integrated circuit devices

• US 7,492,188 B2
• Filed: 07/30/2007
• Issued: 02/17/2009
• Est. Priority Date: 03/04/1999
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schleicher, James, Pedersen, Bruce, Patel, Rakesh, Shumarayev, Sergey, Mendel, David W., Huang, Wei-Jen, Leaver, Andrew, Kazarian, Peter J., Hutton, Michael, Ngai, Tony, Park, Jim, Maruri, Victor
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/888,317
• Publication Number:
  US 20080074143A1
• Time in Patent Office: 568 Days
• Field of Search: 326/39, 326/41, 326/47, 326/101, 326 37- 38
• US Class Current: 326/41
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Claims

1. An integrated circuit device, comprising:

a multi-dimensional interconnection network; and

a plurality of input/out (I/O) cells located within the multi-dimensional interconnection network, each having a plurality of input terminals and at least one output terminal, wherein;

a first subset of conductors is configured to form part of a normal-speed portion of the interconnection network; and

a second subset of conductors is configured to form part of a second high-speed portion of the interconnection network, wherein each of the conductors of the high-speed portion is programmable to make at least part of a connection between the output terminal of substantially any one of the I/O cells and at least one of the input terminals of substantially any of the I/O cells.

2. The device defined in claim 1, wherein the first subset in each of the I/O cells includes more of the conductors of that I/O cell than the second subset of that I/O cell includes.

3. The device defined in claim 2, wherein the first subset in each of the I/O cells includes in the range from about 67% to about 80% of the conductors in that I/O cell.

4. The device defined in claim 1, wherein the high-speed portion includes a plurality of interconnection conductors, each I/O cell being associated with circuitry that can programmably select any of at least a subplurality of the output terminals of the I/O cells for connection to that interconnection conductor.

5. The device defined in claim 1, wherein the high-speed portion is configured to provide signal routing which is alternative to routing for the same connection through the normal-speed portion, the alternative routing through the high-speed portion being substantially faster than routing through the normal-speed portion to which the alternative routing is alternative.

6. The device defined in claim 1, wherein the I/O cells are disposed on the device in a two-dimensional array of intersecting rows and columns of the I/O cells, wherein the interconnection network includes a group of horizontal interconnection conductors associated with an extending along each of the rows, a group of vertical interconnection conductors associated with and extending along each of the columns, and programmable connectors configured to selectively interconnect horizontal and vertical interconnection conductors, and wherein a first subset of the conductors in each of the groups is configured to form part of the normal-speed portion of the interconnection network, and a second subset of the conductors in each of the groups is configured to form part of the high-speed portion of the interconnection network.

7. The device defined in claim 6, wherein the programmable connectors include a first subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the first subsets of the conductors but not horizontal and vertical interconnection conductors in the second subsets of the conductors.

8. The device defined in claim 6, wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.

9. The device defined in claim 8, wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.

10. The device defined in claim 9, wherein each of the programmable connectors includes a signal driver, and wherein the signal drivers of the second subset of the connectors are larger and more powerful than the signal drivers of the first subset of conductors.

11. The device defined in claim 6, wherein the conductors in the second subset of the conductors in each of the groups are wider than the conductors in the first subset of the conductors in that group.

12. The device defined in claim 6, wherein the conductors in the second subset of the conductors in each of the groups are spaced more widely from other conductors than the conductors in the first subset of the conductors in that group.

13. The device defined in claim 1, wherein the interconnection network further includes programmable circuitry configured to apply signals from at least some of the I/O cells to at least one input terminal of that I/O cell, the programmable circuitry including connection paths that are more direct for signals from conductors in the second subset of the conductors associated with that I/O cell than for signals from conductors in the first subset of the conductors associated with that I/O cell.

14. The device defined in claim 6, further comprising:

a plurality of high-speed regional interconnection conductors associated with and extending along each of a plurality of subsets of multiple adjacent I/O cells in each of the rows.

15. The device defined in claim 14, wherein each of the high-speed regional interconnection conductors is configured for programmable connection to the output terminal of the one of the associated I/O cells that is approximately centered amid the multiple adjacent I/O cells associated with the high-speed regional interconnection conductor.

16. The device defined in claim 15, wherein each of the high-speed regional interconnection conductors associated with each I/O cell is programmably connectable to at least one input terminal of substantially any of the I/O cells associated with the high-speed local interconnection conductor.

17. The device defined in claim 6, further comprising a bridging interconnection conductor associated with each adjacent pair of I/O cells in each column and configured to convey a signal from one of the I/O cells in the associated pair only to programmable output circuitry associated with the other I/O cell in that pair, the output circuitry being configured to selectively apply a signal on the bridging interconnection conductor to the interconnection network in lieu of the signal from the output terminal of the other I/O cell in that pair.

18. A digital processing system comprising:

processing circuitry;

a memory coupled to the processing circuitry; and

an integrated circuit device as defined in claim 1 coupled to the processing circuitry and the memory.

19. A printed circuit board on which is mounted an integrated circuit device as defined in claim 1.

20. The device defined in claim 19, further comprising:

a memory mounted on the printed circuit board and coupled to the integrated circuit device.

21. The device defined in claim 1, wherein the integrated circuit device comprises a programmable logic device.

22. The device defined in claim 1, further comprising a plurality of logic regions arranged in the multi-dimensional interconnection network.