Memory array having a programmable word length, and method of operating same

• US 7,492,632 B2
• Filed: 03/15/2007
• Issued: 02/17/2009
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Carman, Eric
• Primary Examiner(s): Auduong, Gene N.
• Application Number:
  US11/724,552
• Publication Number:
  US 20070285982A1
• Time in Patent Office: 705 Days
• Field of Search: 365/177, 365/149, 365/174, 365/230.06, 365/195, 365/196
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.

Claims

1. An integrated circuit device comprising:

a memory cell array including;

a plurality of word lines;

a plurality of source lines;

a plurality of bit lines; and

a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes;

a first region coupled to an associated source line;

a second region coupled to an associated bit line;

a body region disposed between the first region and the second region, wherein the body region is electrically floating;

a gate disposed over the body region and coupled to an associated word line; and

wherein each memory cell includes a plurality of data states, including;

(i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor; and

(ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor;

first circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and

(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation.

2. The integrated circuit device of claim 1 wherein the number of memory cells of the first group of memory cells corresponds to a word length of the memory cell array.

3. The integrated circuit device of claim 2 further including word length selection circuitry to store data which is representative of the word length.

4. The integrated circuit device of claim 1 wherein the write de-select control signals include:

(i) a first temporally changing signal applied to the gate of each memory cell of the second group of memory cells, (ii) a second temporally changing signal applied to the first region of each memory cell of the second group of memory cells, and (iii) a third temporally changing signal applied to the second region of each memory cell of the second group of memory cells.

5. The integrated circuit device of claim 4 wherein the write control signals include:

(i) the first temporally changing signal applied to the gate of each memory cell of the first group of memory cells, (ii) the second temporally changing signal applied to the first region of each memory cell of the first group of memory cells, and (iii) a fourth temporally changing signal applied to the second region of each memory cell of the first group of memory cells.

6. The integrated circuit device of claim 1 wherein the write de-select control signals include:

(i) a first temporally changing signal applied to the gate of each memory cell of the second group of memory cells, (ii) a second temporally changing signal applied to the first region of each memory cell of the second group of memory cells, and (iii) a third signal having a substantially constant voltage amplitude applied to the second region of each memory cell of the second group of memory cells.

7. The integrated circuit device of claim 6 wherein the write control signals include:

(i) the first temporally changing signal applied to the gate of each memory cell of the first group of memory cells, (ii) the second temporally changing signal applied to the first region of each memory cell of the first group of memory cells, and (iii) a fourth temporally changing signal applied to the second region of each memory cell of the first group of memory cells.

8. The integrated circuit device of claim 1 further including second circuitry, coupled to each memory cell of the first row of memory cells, to perform a read operation with respect to memory cells of the first row of memory cells by concurrently applying:

(i) read control signals to the first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and (ii) read de-select control signals to the second group of memory cells of the first row of memory cells to inhibit the read operation with respect to the second group of memory cells of the first row of memory cells and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

9. The integrated circuit device of claim 8 wherein the read control signals include a signal applied to the gate, a signal applied to the first region, and a signal applied to the second region of the electrically floating body transistor of each memory cell of the first group of memory cells to cause, force and/or induce a read bipolar transistor current which is representative of the data state of each memory cell of the first group of memory cells of the first row of memory cells.

10. The integrated circuit device of claim 9 wherein the second circuitry determines the data state of the memory cell substantially based on the read bipolar transistor current.

11. The integrated circuit device of claim 9 wherein the second circuitry includes a plurality of sense amplifiers.

12. The integrated circuit device of claim 1 wherein the write control signals include control signals to write the first data state and wherein, in response to the control signals to write the first data state into a predetermined memory cell of the first row of memory cells, the electrically floating body transistor of the predetermined memory cell of the first row of memory cells generates a bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor of the predetermined memory cell of the first row of memory cells.

13. The integrated circuit device of claim 1 wherein the each memory cell includes a third data state which is representative of a third charge in the body region of the electrically floating body transistor

14. The integrated circuit of claim 1 wherein the first circuitry includes means for performing a write operation with respect to memory cells of the first row of memory cells by concurrently applying:

(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and

(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation.

15. An Integrated circuit device comprising;

a semiconductor memory array including;

a plurality of word lines;

a plurality of source lines;

a plurality of bit lines; and

a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes;

a first region coupled to an associated source line;

a second region coupled to an associated bit line;

a body region disposed between the first region and the second region, wherein the body region is electrically floating;

a gate disposed over the body region and coupled to an associated word line; and

wherein each memory cell includes at least two data states, including;

(i) a first data state which is representative of a first charge in the body region of the associated electrically floating body transistor; and

(ii) a second data state which is representative of a second charge in the body region of the associated electrically floating body transistor; and

circuitry, coupled to each memory cell of a first row of memory cells, to perform a read operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) read control signals to a first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and

(ii) read de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the read operation with respect to the second group of memory cells of the first row of memory cells and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

16. The integrated circuit device of claim 15 wherein the read control signals include a signal applied to the gate, a signal applied to the first region, and a signal applied to the second region of the electrically floating body transistor of each memory cell of the first group of memory cells to cause, force and/or induce a read bipolar transistor current which is representative of the data state of each memory cell of the first group of memory cells of the first row of memory cells.

17. The integrated circuit device of claim 15 wherein the circuitry determines the data state of the memory cell substantially based on the read bipolar transistor current.

18. The integrated circuit device of claim 15 wherein the circuitry includes a plurality of sense amplifiers.

19. The integrated circuit device of claim 15 further including write circuitry, coupled to each memory cell of the first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying:

(i) write control signals to the first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and

(ii) write de-select control signals to the second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation; and

wherein the write control signals include control signals to write the first data state and wherein, in response to the control signals to write the first data state into a predetermined memory cell of the first row of memory cells, the electrically floating body transistor of the predetermined memory cell of the first row of memory cells generates a bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor of the predetermined memory cell of the first row of memory cells.

20. The integrated circuit device of claim 15 wherein the number of memory cells of the first group of memory cells corresponds to a word length of the memory cell array.

21. The integrated circuit device of claim 20 further including word length selection circuitry to store data which is representative of the word length.

22. The integrated circuit of claim 15 wherein the circuitry includes means for performing a read operation with respect to memory cells of the first row of memory cells by concurrently applying:

(i) read control signals to a first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and

(ii) read de-select control signals to a second group of memory calls of the first row of memory cells to inhibit the read operation with respect to the second group of memory cells of the first row of memory cells, and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

23. An integrated circuit device comprising;

a semiconductor memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the semiconductor memory array, comprising;

a plurality of word lines;

a plurality of source lines;

a plurality of bit lines; and

a plurality of dynamic random access memory cells disposed in or on the semiconductor region or layer and arranged in a matrix of rows and columns, each dynamic random access memory cell includes at least one transistor having;

a first region coupled to an associated source line;

a second region coupled to an associated bit line;

a body region disposed between the first region and the second region, wherein the body region is electrically floating;

a gate disposed over the body region and coupled to an associated word line; and

wherein each memory cell includes at least two data states, including;

(i) a first data state which is representative of a first charge in the body region of the associated electrically floating body transistor; and

(ii) a second data state which is representative of a second charge in the body region of the associated electrically floating body transistor;

first circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and

(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and

thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation; and

second circuitry, coupled to each memory cell of the first row of memory cells, to perform a read operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) read control signals to the first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and

(ii) read de-select control signals to the second group of memory cells of the first row of memory cells to inhibit the read operation with respect thereto, and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.

24. The integrated circuit device of claim 23 wherein the read control signals include a signal applied to the gate, a signal applied to the first region, and a signal applied to the second region of the electrically floating body transistor of each memory cell of the first group of memory cells to cause, force and/or induce a read bipolar transistor current which is representative of the data state of each memory cell of the first group of memory cells of the first row of memory cells.

25. The integrated circuit device of claim 23 wherein the second circuitry determines the data state of the memory cell substantially based on the read bipolar transistor current.

26. The integrated circuit device of claim 23 wherein the second circuitry includes a plurality of sense amplifiers.

27. The integrated circuit device of claim 23 wherein the write control signals include control signals to write the first data state and wherein, in response to the control signals to write the first data state into a predetermined memory cell of the first row of memory cells, the electrically floating body transistor of the predetermined memory cell of the first row of memory cells generates a bipolar transistor current which substantially provides the first charge in the body region of the electrically floating body transistor of the predetermined memory cell of the first row of memory cells.

28. The integrated circuit device of claim 23 wherein the each memory cell includes a third data state which is representative of a third charge in the body region of the electrically floating body transistor.

29. The integrated circuit device of claim 23 wherein the number of memory cells of the first group of memory cells corresponds to a word length of the memory cell array.

30. The integrated circuit device of claim 29 further including word length selection circuitry to store data which is representative of the word length.

31. The integrated circuit of claim 23 wherein:

the first circuitry includes means for performing a write operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and

(ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation; and

the second circuitry includes means for performing a read operation with respect to memory cells of the first row of memory cells by concurrently applying;

(i) read control signals to the first group of memory cells of the first row of memory cells to read the data state of each memory cell of the first group of memory cells, and

(ii) read de-select control signals to the second group of memory cells of the first row of memory cells to inhibit the read operation with respect thereto, and thereby inhibit reading the data state of each memory cell of the second group of memory cells during the read operation.