Flash EEprom system

• US 7,492,660 B2
• Filed: 04/15/2003
• Issued: 02/17/2009
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US10/414,718
• Publication Number:
  US 20030206449A1
• Time in Patent Office: 2,135 Days
• Field of Search: 365/230.03, 365/230.01, 365/185.11, 365/185.33, 711/202, 711/209, 711/221
• US Class Current: 365/230.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of accessing a flash memory array, comprising:

a) receiving a logical address at a controller for the flash memory array and determining that the logical address corresponds to a defective memory location;

b) determining, at the controller, a block of the flash memory array to access based on the received logical address, the flash memory array being divided into a plurality of blocks, each block for storing data and having logical address to physical address conversion information;

c) obtaining the conversion information from the determined block;

d) storing the obtained conversion information for the determined block at the controller; and

e) performing a memory access operation on the flash memory array using the controller based on the received logical address and the stored conversion information.

2. The method of claim 1, wherein each physical address in the conversion information for each block identifies at least one sector in the block.

3. The method of claim 1, wherein

the step a) receives a read command associated with the received logical address;

and

the step e) includes the following sub-steps when the step a) receives the read command,

e1) determining if the received logical address matches a logical address in the stored conversion information,

e2) identifying a physical address associated with the received logical address from the stored conversion information if the step e1) determines a match exists,

e3) accessing data stored in the identified physical address, and

e4) outputting the accessed data from the controller.

4. The method of claim 3, wherein the step e) further includes the following sub-step when the step a) receives the read command,

e5) outputting an error signal if the step b) does not determine a match exists.

5. A device for accessing a 0ash memory array, comprising:

a selecting unit receiving a logical address for the flash memory array, determining that the logical address corresponds to a defective location, and determining a block of the flash memory array to access based on the received logical address, the flash memory array being divided into a plurality of blocks, each block for storing data and having logical address to physical address conversion information;

at least one storage device for storing conversion information;

a control unit receiving the received logical address, obtaining the conversion information from the determined block, storing the obtained conversion information for the determined block in the storage device, and performing a memory access operation on the flash memory array based on the received logical address and the stored conversion information, and determining that the logical address corresponds to a defective location.

6. The device of claim 5, wherein each physical address in the conversion information for each block identifies at least one sector in the block.

7. The device of claim 5, wherein

the control unit receives a read command associated with the received logical address, and in response thereto determines if the received logical address matches a logical address in the stored conversion information, identifies a physical address associated with the received logical address from the stored conversion information if a match exists, accesses data stored in the identified physical address, and outputs the accessed data.

8. The device of claim 5 wherein the storage device is a buffer.

9. The device of claim 5, wherein the control unit includes the storage device.

10. A method of accessing a flash memory array, comprising:

a) receiving a logical address at a controller for the flash memory array and determining that the logical address corresponds to a defective memory location;

b) determining, at the controller, a division of the flash memory array to access based on the received logical address, the flash memory array being divided into a plurality of divisions, each division for storing data and having logical address to physical address conversion information;

c) obtaining the conversion information from the determined division;

d) storing the obtained conversion information for the determined division at the controller; and

e) performing a memory access operation on the flash memory array using the controller based on the received logical address and the stored conversion information.

11. The method of claim 10, wherein each physical address in the conversion information for each division identifies at least one sector in the division.

12. The method of claim 10, wherein

the step a) receives a read command associated with the received logical address;

and

the step e) includes the following sub-steps when the step a) receives the read command,

e1) determining if the received logical address matches a logical address in the stored conversion information,

e2) identifying a physical address associated with the received logical address from the stored conversion information if the step e1) determines a match exists,

e3) accessing data stored in the identified physical address, and

e4) outputting the accessed data from the controller.

13. The method of claim 12, wherein the step e) further includes the following sub-step when the step a) receives the read command,

e5) outputting an error signal if the step b) does not determine a match exists.

14. The method of claim 10, wherein said division corresponds to the unit of erase of said flash memory array.

15. A device for accessing a flash memory array, comprising:

a selecting unit receiving a logical address for the flash memory array, determining that the logical address corresponds to a defective location, and determining a division of the flash memory array to access based on the received logical address, the flash memory array being divided into a plurality of divisions, each division for storing data and having logical address to physical address conversion information;

at least one storage device for storing conversion information;

a control unit receiving the received logical address, obtaining the conversion information from the determined division, storing the obtained conversion information for the determined division in the storage device, and performing a memory access operation on the flash memory array based on the received logical address and the stored conversion information.

16. The device of claim 15, wherein each physical address in the conversion information for each division identifies at least one sector in the division.

17. The device of claim 15, wherein

the control unit receives a read command associated with the received logical address, and in response thereto determines if the received logical address matches a logical address in the stored conversion information, identifies a physical address associated with the received logical address from the stored conversion information if a match exists, accesses data stored in the identified physical address, and outputs the accessed data.

18. The device of claim 15 wherein the storage device is a buffer.

19. The device of claim 15, wherein the control unit includes the storage device.

20. The device of claim 15, wherein said division corresponds to the unit of erase of said flash memory array.