PMA RX in coarse loop for high speed sampling

• US 7,493,095 B2
• Filed: 04/25/2007
• Issued: 02/17/2009
• Est. Priority Date: 09/11/2003
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chuang, Jerry, Black, William C., Irwin, Scott A.
• Primary Examiner(s): Tran; Pablo N
• Application Number:
  US11/796,111
• Publication Number:
  US 20070201541A1
• Time in Patent Office: 664 Days
• Field of Search: 455255-260, 4551791-1831, 455313-318, 455/326, 455207-209, 455/219, 4551891-1923, 455/84, 455323-324, 455/265, 455/327, 455297-298, 455/552.1, 375/221, 375/316, 375/355, 375/347, 348725-726, 348/731, 348/735, 331/16, 331/17, 331/117.R, 331/177.V, 331/179
• US Class Current: 455/260
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Claims

1. A transceiver for processing high data rate serial data, comprising:

transceiver circuitry for transmitting and receiving the high data rate serial data;

phase-locked loop circuitry further including a selectable coarse loop PLL and a selectable fine loop PLL, wherein;

the selectable coarse loop PLL for producing a coarse error signal reflecting a difference between a reference signal and a coarse loop feedback signal; and

the selectable fine loop PLL for producing a fine loop error adjustment signal based upon a difference in a recovered clock and the high data rate serial data;

a loop filter for producing an error signal based on at least one of the fine loop error adjustment signal from a fine loop charge pump and the coarse error signal from a coarse loop charge pump;

a controlled oscillation module for producing a receiver clock in the form of an oscillating signal based on the error signal produced by the loop filter;

a divider for dividing the oscillating signal to produce the recovered clock to a phase detector;

a selectable coarse loop selection switch coupled between the coarse loop charge pump and the loop filter;

coarse loop logic circuitry for providing control commands to couple the selectable coarse loop PLL to the loop filter based upon one of a sample mode signal or a detected difference between a reference clock and the coarse loop feedback signal;

a selectable fine loop selection switch coupled between the fine loop charge pump and the loop filter; and

mode determination logic external to the fine loop PLL and coarse loop PLL coupled to produce mode switching signals to selectively switch the selectable coarse loop PLL and selectable fine loop PLL into and out of coupling according to defined operational logic within the mode determination logic.

2. The transceiver of claim 1 wherein the mode switching signals comprise a sample mode signal and a logical opposite of the sample mode signal.

3. The transceiver of claim 1 wherein the mode determination logic produces the mode switching signals responsive to one of an externally specified automatic mode, a sample mode, and a receive mode of operation.

4. The transceiver of claim 3 wherein the mode determination logic, when in a sample mode of operation, selectively de-couples the selectable fine loop PLL and couples the selectable coarse loop PLL as long as the transceiver is in the sample mode of operation.

5. The transceiver of claim 3 wherein the transceiver, when in the automatic mode of operation further operates according to an initial (coarse) calibration mode of operation and a final (fine) calibration mode of operation.

6. The transceiver of claim 5 wherein the automatic mode of operation is a default mode of operation.

7. The transceiver of claim 5 wherein the error signal produced by the loop filter is a voltage signal and further wherein the controlled oscillation module produces the corresponding oscillation characterized by an oscillation frequency that is a function of a magnitude of the voltage signal.

8. The transceiver of claim 5 wherein the mode determination logic prompts the phase-locked loop circuitry to lock to a local reference for data sampling operations responsive to a mode selection signal received from an external source.

9. The transceiver of claim 5 wherein the mode determination logic prompts the phase-locked loop circuitry to lock to the received high data rate serial data responsive to the mode selection signal received from the external source.

10. The transceiver of claim 5 wherein the mode determination logic, when in the initial calibration mode, produces a fine loop calibration signal to de-couple the selectable fine loop PLL and a coarse loop calibration signal to couple the selectable coarse loop PLL.

11. The transceiver of claim 10 wherein the mode determination logic selectively couples the selectable fine loop PLL after a specified period.

12. The transceiver of claim 11 wherein the mode determination logic selectively de-couples the selectable coarse loop PLL after the specified period.

13. The transceiver of claim 10 wherein the mode determination logic selectively couples the selectable fine loop PLL after determining that a recovered clock derived from an oscillation signal corresponding to the coarse error signal as produced by the selectable coarse loop PLL is within the specified degree of accuracy relative to the received high data rate serial data.

14. The transceiver of claim 13 wherein the mode determination logic selectively de-couples the selectable coarse loop PLL.