Optimization of SMI handling and initialization

• US 7,493,435 B2
• Filed: 10/06/2003
• Issued: 02/17/2009
• Est. Priority Date: 10/06/2003
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kobayashi, Grant H., Cooper, Barnes
• Primary Examiner(s): Auve; Glenn A
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US10/681,446
• Publication Number:
  US 20050086547A1
• Time in Patent Office: 1,961 Days
• Field of Search: 710/260, 710/269, 710/8, 710/261, 710/14, 710/267, 709/318, 711/163, 711/170, 712/31, 713/310, 713/1, 713/300, 713/323, 713/2, 713/100, 713/324, 707/10, 714/726, 455/418, 718/100
• US Class Current: 710/260
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

Claims

1. A method comprising:

receiving a first system management interrupt (SMI) with a first and a second processor;

handling the first SMI with the first processor;

generating a wake-up signal with the first processor after receiving the first SMI, wherein the wake-up signal references a first memory address of a default SMI handler;

receiving the wake-up signal with the second processor;

awakening the second processor, based on the wake-up signal from the first processor; and

handling the first SMI with the second processor.

2. The method of claim 1, wherein the first and second processors are logical processors, and wherein the first logical processor includes a first thread and the second logical processor includes a second thread.

3. The method of claim 1, wherein the first and second processors are physical processors.

4. The method of claim 1, wherein handling the first SMI with a first processor comprises:

executing the default SMI handler located at the first memory address.

5. The method of claim 4, wherein the wake-up signal is a startup inter processor interrupt (SIPI) signal.

6. The method of claim 5, wherein the first memory address is aligned.

7. The method of claim 6, wherein the first memory address is 4 k aligned.

8. The method of claim 5, wherein handling the first SMI with the second processor comprises executing the default SMI handler with the second processor.

9. The method of claim 8, wherein handling the first SMI with the second processor further comprises patching an instruction pointer to a second memory address.

10. The method of claim 9, wherein the second memory address is a non-aligned address.

11. The method of claim 10, further comprising:

executing code at the second memory address after handling the first SMI with the second processor.

12. A method comprising:

receiving a first system management interrupt (SMI);

executing code at a first memory location with a first processor in response to the first SMI;

generating a wake-up signal with the first processor;

awakening a second processor, based on a wake-up signal from the first processor; and

executing the code from the first memory location with the second processor, in response to the first SMI after awakening the second processor.

13. The method of claim 12, wherein the wake-up signal is based on the first memory location.

14. The method of claim 13, wherein the code at the first memory location is default SMI handling code.

15. The method of claim 14, wherein the first memory location is located in conventional memory.

16. The method of claim 15, wherein the first memory location is aligned.

17. The method of claim 12, wherein both the first and second processors are logical processors located on the same die.

18. The method of claim 12, wherein the first and second processors are physical processors located on separate packages.

19. The method of claim 12, further comprising patching an instruction pointer for the second processor to a second memory location.

20. The method of claim 19, wherein the second memory location is a non-aligned location.

21. The method of claim 20, further comprising:

executing code at the second memory location after patching the instruction pointer to the second memory location.

22. The method of claim 12, further comprising generating the SMI before receiving the first SMI.

23. The method of claim 22, wherein generating the SMI comprises changing the logic level of a pin coupled to a controller hub.

24. The method of claim 22, wherein an APIC is used to generate the SMI.

25. The method of claim 24, wherein the APIC is located in the first processor.

26. A method comprising:

executing system management interrupt (SMI) code with a first processor to handle a SMI for the first processor;

checking if the SMI is a software generated SMI; and

executing the SMI code to handle the SMI for a second processor, if the SMI is software generated.

27. The method of claim 26, wherein the first processor executes the SMI code to handle the SMI for the second processor, if the SMI is software generated.

28. The method of claim 26, wherein the second processor executes the SMI code to handle the SMI for the second processor, if the SMI is software generated.

29. The method of claim 26, wherein the first processor has a first system management base (SMBase) address.

30. The method of claim 29, wherein the second processor has a second SMBase address.

31. The method of claim 30, wherein said SMI code is located at first memory location, which has an offset from the first SMBase address.

32. The method of claim 31, wherein executing said SMI code to handle the SMI for the second processor comprises:

changing a target SMBase from the first SMBase to the second SMBase; and

executing the SMI code using the second SMBase as the target SMBase.

33. The method of claim 32, further comprising returning the target SMBase of the SMI handler to the first SMBase after executing the SMI code to handle the SMI for the second processor.

34. An apparatus comprising:

a controller to generate a first system management interrupt (SMI);

a first logical processor, coupled to the controller, to receive the first SMI, to handle the first SMI and to generate a wake-up signal after receiving the first SMI, wherein the wake-up signal references a first memory address of a default SMI handler; and

a second logical processor, coupled to the controller, to handle the first SMI after the wake-up signal is received from the first logical processor.

35. The apparatus of claim 34, wherein handling the first SMI with the first logical processor comprises executing the default SMI handler with the first logical processor.

36. The apparatus of claim 35, wherein the first memory address is 1 k aligned.

37. The apparatus of claim 35, wherein handling the first SMI with the second logical processor comprises executing the default SMI handler with the second logical processor.

38. The apparatus of claim 37, wherein handling the first SMI with the second logical processor further comprises patching an instruction pointer to a second memory address.

39. A system comprising:

a controller hub to generate a first system management interrupt (SMI);

a memory to hold code beginning at a first memory address;

a first processor coupled to the controller hub to receive the first SMI and to handle the first SMI, wherein the first processor is to execute the code beginning at the first memory address to handle the first SMI and is to generate a wake-up signal after receiving the first SMI; and

a second processor coupled to the controller hub to receive the first SMI, to be woken up in response to receiving the wake-up signal, and to handle the first SMI after receiving the wake-up signal, wherein the second processor is to execute the code beginning at the first memory address to handle the first SMI.

40. The system of claim 39, wherein the first and second processors are logical processors on the same die.

41. The system of claim 39, wherein the first and second processors are physical processors located on separate packages.

42. The system of claim 39, wherein a pin is toggled on the controller hub to generate the first SMI.

43. The system of claim 39, wherein boot code is executed by the controller hub to generate the first SMI.

44. The system of claim 39, wherein the code beginning at the first memory address includes SMI handling code.

45. The system of claim 44, wherein the wake-up signal includes a vector referencing the first memory address.

46. The system of claim 45, wherein handling the first SMI with the second processor after receiving the wake-up signal further comprises setting a pointer to a second memory address.

47. The system of claim 46, wherein the second processor, upon resuming from handling the SMI, executes code at the second memory address.

48. A system comprising:

a memory to hold system management interrupt (SMI) code beginning at a first memory address;

a first logical processor coupled to the memory to execute the SMI code beginning at the first memory address to handle an SMI for the first logical processor in response to receiving the SMI; and

a second logical processor coupled to the memory to execute the SMI code beginning at the first memory address to handle the SMI for the second logical processor in response to the SMI being software generated.

49. The system of claim 48, wherein the first logical processor is associated with a first system management base (SMBase) address.

50. The system of claim 49, wherein the second logical processor is associated with a second SMBase address.

51. The system of claim 50, wherein the first memory address has an offset from the first SMBase address.

52. The system of claim 51, wherein a target SMBase referenced by the SMI code, by default, is the first SMBase address.

53. The system of claim 52, wherein the target SMBase is changed to the second SMBase address before the second logical processor executes the SMI code.