Hardware-error tolerant computing

• US 7,493,516 B2
• Filed: 02/28/2006
• Issued: 02/17/2009
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T., Wood, Lowell L. Jr., Hillis, W. Daniel, Ferren, Bran
• Primary Examiner(s): Beausoliel; Robert
• Assistant Examiner(s): Arcos; Jeison C
• Application Number:
  US11/364,130
• Publication Number:
  US 20070050659A1
• Time in Patent Office: 1,085 Days
• Field of Search: 714/15, 714/16, 714/17
• US Class Current: 714/10
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

Claims

1. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting the adjustable operating parameter in substantial conformity with an error-tolerant performance criterion that corresponds to 0 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

adjustable operating parameter).

2. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor clock frequency in substantial conformity with 0 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor clock frequency).

3. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor clock frequency in substantial conformity with ±

0.05 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor clock frequency).

4. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor clock frequency in substantial conformity with ±

0.10 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor clock frequency).

5. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor clock frequency in substantial conformity with ±

0.20 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor clock frequency).

6. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor voltage to substantially minimize

a time to complete an execution of the sequence of instructions.

7. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting a processor clock frequency in substantial conformity with

0 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor voltage).

8. A method implemented in a computerized system, the method comprising:

detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and

changing at least one of a voltage of the processor subsystem and/or a processor clock frequency based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions.

9. A method implemented in a computerized system, the method comprising:

detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and

changing a processor clock frequency in substantial conformity with 0 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor clock frequency).

10. A method implemented in a computerized system, the method comprising:

detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and

changing a processor clock frequency in substantial conformity with 0 =(Δ

time to complete an execution of the sequence of instructions) divided by (Δ

processor voltage).