Continuous application and decompression of test patterns to a circuit-under-test

• US 7,493,540 B1
• Filed: 07/20/2000
• Issued: 02/17/2009
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Jansuz, Mukherjee, Nilanjan, Tyszer, Jerzy, Kassab, Mark
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US09/620,021
• Time in Patent Office: 3,134 Days
• Field of Search: 714/729, 714/727, 714/733, 714/734, 714/724, 714/728, 714/736, 714/738, 714/726
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

Claims

1. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided;

applying the decompressed test pattern to scan chains of the circuit-under-test; and

providing the compressed test pattern through input channels to a circuit-under-test, the number of input channels being fewer than the number of scan chains to which the decompressed pattern is applied.

2. The method of claim 1 wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern, and wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XNOR operation.

3. The method of claim 1, wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern.

4. The method of claim 3, wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

5. The method of claim 1, wherein the compressed test pattern is a deterministic test pattern.

6. The method of claim 1, wherein the providing and decompressing occur within the circuit-under-test.

7. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein the compressed test pattern is provided at a lower clock rate and the compressed test pattern is decompressed and applied synchronously at a higher clock rate.

8. The method of claim 7, wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern.

9. The method of claim 8, wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

10. The method of claim 7, wherein the compressed test pattern is a deterministic test pattern.

11. The method of claim 7, wherein the providing and decompressing occur within the circuit-under-test.

12. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein the compressed pattern is provided and decompressed at a higher clock rate and the decompressed pattern is applied synchronously at a lower clock rate.

13. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein decompressing the compressed test pattern comprises generating during a time period a greater number of decompressed test pattern bits than the number of compressed test pattern bits provided during the same time period.

14. The method of claim 13 wherein the greater number of bits is generated by providing a greater number of outputs for decompressed test pattern bits than the number of inputs to which the compressed test pattern bits are provided.

15. The method of claim 13 wherein the greater number of bits is generated by generating the decompressed test pattern bits at a higher clock rate than the clock rate at which the compressed test pattern bits are provided.

16. The method of claim 13, wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern.

17. The method of claim 16, wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

18. The method of claim 13, wherein the compressed test pattern is a deterministic test pattern.

19. The method of claim 13, wherein the providing and decompressing occur within the circuit-under-test.

20. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein applying the decompressed test pattern to the scan chains comprises applying during a time period a greater number of decompressed test pattern bits to the scan chains than the number of compressed test pattern provided during the same time period.

21. The method of claim 20, wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern.

22. The method of claim 21, wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

23. The method of claim 20, wherein the compressed test pattern is a deterministic test pattern.

24. The method of claim 20, wherein the providing and decompressing occur within the circuit-under-test.

25. A circuit comprising:

a decompressor adapted to receive a compressed test pattern of bits and decompress the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received;

circuit logic; and

scan chains for testing the circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern,

wherein the decompressor comprises a linear finite state machine adapted to receive the compressed test pattern, wherein the decompressor includes a phase shifter coupled between the linear finite state machine and the scan chains, and wherein the phase shifter comprises an array of XNOR gates.

26. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided;

applying the decompressed test pattern to scan chains of the circuit-under-test; and

loading an intermediate register with the compressed test pattern, the intermediate register positioned between a decompressor, which is performing the decompressing, and automated test equipment which is providing the compressed test pattern.

27. A circuit comprising:

a decompressor adapted to receive a compressed test pattern of bits and decompress the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received;

circuit logic;

scan chains for testing the circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern; and

automated test equipment coupled externally to the circuit and an intermediate register coupled between the automated test equipment and the decompressor.

28. The circuit of claim 27, wherein the intermediate register receives compressed test patterns from the automated test equipment and provides the compressed test patterns to the decompressor.

29. A circuit comprising:

a decompressor adapted to receive a compressed test pattern of bits and decompress the test pattern into a decompressed test pattern of bits, the decompressor having a plurality of input channels and a plurality of outputs, the input channels receiving in parallel the bits of the compressed test pattern;

circuit logic;

scan chains for testing the circuit logic, the scan chains coupled to the outputs of the decompressor and adapted to receive the decompressed test pattern in parallel; and

automated test equipment coupled externally to the circuit and an intermediate register positioned between the automated test equipment and the decompressor.

30. A circuit comprising:

a linear finite state machine having input logic gates adapted to logically combine bits stored within the machine with bits received from a compressed test pattern, the state machine generating therefrom a series of bits;

a phase shifter coupled to the linear finite state machine, the phase shifter adapted to logically combine two or more bits generated by the linear finite state machine to produce a decompressed pattern of bits;

scan chains coupled to the phase shifter and adapted to receive therefrom the decompressed test pattern; and

automated test equipment coupled externally to the circuit and an intermediate register positioned between the automated test equipment and the linear finite state machine.

31. A circuit comprising:

a linear finite state machine having input logic gates adapted to logically combine bits stored within the machine with bits received from a compressed test pattern, the state machine generating therefrom a series of bits;

a phase shifter coupled to the linear finite state machine, the phase shifter adapted to logically combine two or more bits generated by the linear finite state machine to produce a decompressed pattern of bits; and

scan chains coupled to the phase shifter and adapted to receive therefrom the decompressed test pattern,

wherein the bits of the compressed test pattern are received while the decompressed pattern of bits are produced.

32. The circuit of claim 31, wherein the number of scan chains is greater than the number of input channels.

33. A circuit comprising:

a linear finite state machine having input logic gates adapted to logically combine bits stored within the machine with bits received from a compressed test pattern, the state machine generating therefrom a series of bits;

a phase shifter coupled to the linear finite state machine, the phase shifter adapted to logically combine two or more bits generated by the linear finite state machine to produce a decompressed pattern of bits; and

scan chains coupled to the phase shifter and adapted to receive therefrom the decompressed test pattern,

wherein the linear state machine receives bits of the compressed test pattern substantially concurrent with the phase shifter producing a decompressed pattern of bits.

34. The circuit of claim 33, wherein the number of scan chains is greater than the number of input channels.

35. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at a same clock rate, and wherein decompressing the compressed test pattern comprises generating one or more bits of the decompressed pattern by logically combining two or more bits of the compressed test pattern.

36. The method of claim 35, wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

37. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

providing a compressed test pattern of bits;

decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and

applying the decompressed test pattern to scan chains of the circuit-under-test,

wherein providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at a same clock rate, and wherein the compressed test pattern is a deterministic test pattern.