Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same

• US 7,494,876 B1
• Filed: 04/21/2005
• Issued: 02/24/2009
• Est. Priority Date: 04/21/2005
• Status: Expired due to Fees

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Lui, Kam Hong, Giles, Frederick Perry
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Nguyen; DiLinh
• Application Number:
  US11/112,403
• Time in Patent Office: 1,405 Days
• Field of Search: 438156-157, 438/138, 438/173, 438/212, 438/268, 438/206, 438136-137, 438/270, 438/197, 438/259, 438/272, 438/589, 257/213, 257/288, 257/327, 257/341, 257/343, 257/330, 257331-332, 257/335, 257/397, 257/513, 257/E27.091, 257/E29.2, 257/E29.201, 257/E21.585
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a trench-gated MIS semiconductor device, a slug of undoped polysilicon is deposited at the bottom of the trench to protect the gate oxide in this area against the high electric fields that can occur in this area. The slug is formed over a thick oxide layer at the bottom of the trench. A process of fabricating the MOSFET includes the steps of growing a thick oxide layer on the sidewalls and bottom of the trench, depositing a polysilicon layer which remains undoped, etching the polysilicon layer to form the plug, etching the exposed portion of the thick oxide layer, growing a gate oxide layer and an oxide layer over the plug, and depositing and doping a polysilicon layer which serves as the gate electrode. In an alternative embodiment, the oxide layer overlying the plug is etched before the gate polysilicon is deposited such that the dopant introduced into the gate polysilicon migrates into the polysilicon plug. In this embodiment, the polysilicon plug is in electrical contact with the gate polysilicon layer and is separated from the drain by the thick oxide layer.

Claims

1. A method of fabricating an MIS device comprising:

forming a trench in a semiconductor chip comprising an N-epi layer atop an N+ substrate, the trench having a sidewall and a bottom, wherein the trench is formed in the N-epi layer and does not extend to the N+ substrate;

growing a first oxide layer on the sidewall and bottom of the trench;

depositing undoped polysilicon in the trench;

etching a portion of the undoped polysilicon to expose a portion of the first oxide layer while leaving a plug of undoped polysilicon at the bottom of the trench;

etching the exposed portion of the first oxide layer to expose a portion of a sidewall of the trench;

growing a gate oxide layer on the exposed portion of the sidewall;

growing a second oxide layer on the undoped polysilicon plug;

depositing a polysilicon layer in the trench that overflows onto a top surface of the N-epi layer, the polysilicon layer for forming a gate and is adjacent to the gate oxide and the second oxide layer; and

etching back the polysilicon layer until its top surface is approximately level with the top surface of the N-epi layer.

2. The method of claim 1 wherein the undoped polysilicon plug is used as an etch stop for the portion of the first oxide layer beneath the undoped polysilicon plug during the etching of the exposed portion of the first oxide layer.

3. The method of claim 1 further comprising doping the polysilicon layer before the etching back.

4. The method of claim 3 further comprising depositing a glass layer above the N-epi layer after the etching back.

5. The method of claim 4 comprising etching the second oxide layer to expose the undoped polysilicon plug before depositing the polysilicon layer such that the polysilicon layer is in contact with the undoped polysilicon plug.

6. The method of claim 5 wherein doping the polysilicon layer causes dopant to enter the undoped polysilicon.

7. The method of claim 1 wherein growing the gate oxide layer and growing the second oxide layer occur substantially simultaneously.

8. The method of claim 1 further comprising forming a P-body region and an N+ source region in the N-epi layer after the etching back.