Manufacturing a semiconductive device using a controlled atomic layer removal process

• US 7,494,882 B2
• Filed: 03/10/2006
• Issued: 02/24/2009
• Est. Priority Date: 03/10/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Vitale, Steven Arthur
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US11/373,662
• Publication Number:
  US 20070212864A1
• Time in Patent Office: 1,082 Days
• Field of Search: 438/286.304, 438/305, 438/531, 438/596, 257/E21.242, 257/E21.158, 257/E21.58
• US Class Current: 438/286
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from the lateral surfaces and the vertical surfaces that are located under the mask to form a target dimension of a semiconductive device structure.

Claims

1. A method for manufacturing a semiconductive device, comprising:

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing thicknesses of one to seven atomic diameters of atoms that comprise said layer from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, each of said thicknesses being equal to about one to seven atomic diameters of atoms that comprise said layer.

2. The method of claim 1, wherein said layer comprises polysilicon.

3. The method of claim 1, wherein said semiconductive device structure is a transistor gate and said target dimension is a gate length.

5. The method of claim 1, wherein said partial etching comprises removing portions of said layer that are not covered by said mask.

6. The method of claim 1, wherein said mask comprises a patterned resist and a patterned hardmask.

7. The method of claim 1, wherein said removing comprises exposing said vertical and lateral surfaces to pulses of fluorine or hydrogen radicals.

9. The method of claim 7, wherein said fluorine or said hydrogen radicals are generated in a plasma using one or more of F₂, NF₃, SF₆, H₂ or CH₄ feed gases.

10. The method of claim 7, wherein said plasma is a down-stream plasma source.

11. The method of claim 7, wherein said fluorine radicals are generated in the absence of plasma from XeF₂ feed gas.

21. The method of claim 1, wherein said removing is accomplished without substantially exposing said lateral surfaces and said vertical surfaces to plasma-generated ions.

4. A method for manufacturing a semiconductive device, comprising:

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing thicknesses of one to several atomic diameters of atoms that comprise said layer from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, each of said thicknesses being equal to about one to several atomic diameters of atoms that comprise said layer, wherein said target dimension is about 40 nanometers or less.

8. A method for manufacturing a semiconductive device, comprising:

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing thicknesses of one to several atomic diameters of atoms that comprise said layer from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, each of said thicknesses being equal to about one to several atomic diameters of atoms that comprise said layer, wherein

said removing comprises exposing said vertical and lateral surfaces to pulses of fluorine or hydrogen radicals, and

individual ones of said pulses are about 1 second or less.

12. A method of manufacturing an integrated circuit comprising:

forming a semiconductive device comprising;

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing atomic layers from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, each of said atomic layers being equal to about one to seven atomic diameters of atoms that comprise said layer; and

forming interconnects to interconnect said semiconductive device to form an operative integrated circuit.

13. The method of claim 12, wherein said layer comprises polysilicon and said semiconductive device structure is a transistor gate.

14. The method of claim 12, wherein said semiconductive device is a MOS transistor.

15. The method of claim 12, wherein said target dimension is a transistor gate length.

17. The method of claim 12, wherein said removing comprises exposing said vertical and lateral surfaces to bursts of fluorine or hydrogen radicals.

19. The method of claim 17, wherein said fluorine or said hydrogen radicals are generated in a plasma using one or more of F₂, NF₃, SF₆, H₂ or CH₄ gases.

20. The method of claim 17, wherein said fluorine radicals are generated in the absence of plasma from XeF₂ gas.

22. The method of claim 12, wherein said removing is accomplished without substantially exposing said lateral surfaces and said vertical surfaces to plasma-generated ions.

16. A method of manufacturing an integrated circuit comprising:

forming a semiconductive device comprising;

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing atomic layers from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, each of said atomic layers being equal to about one to several atomic diameters of atoms that comprise said layer; and

forming interconnects to interconnect said semiconductive device to form an integrated circuit, wherein said target dimension is about 40 nanometers or less.

18. A method of manufacturing an integrated circuit comprising:

forming a semiconductive device comprising;

forming a mask for a semiconductive device structure over a layer of a semiconductor substrate;

partially etching said layer to form lateral and vertical surfaces; and

removing atomic layers from said lateral surfaces and said vertical surfaces that are located under said mask to form a target dimension of a semiconductive device structure, wherein said removing comprises exposing said vertical and lateral surfaces to bursts of fluorine or hydrogen radicals, and individual ones of said bursts are less than about 1 second.