Strained dislocation-free channels for CMOS and method of manufacture

• US 7,495,291 B2
• Filed: 02/22/2005
• Issued: 02/24/2009
• Est. Priority Date: 10/20/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US11/061,445
• Publication Number:
  US 20050139930A1
• Time in Patent Office: 1,463 Days
• Field of Search: 257/369, 257/351, 257/49, 257/371, 257/350, 257/338, 257/E29.047, 257/E29.027, 257/E29.025, 257/E29.021
• US Class Current: 257/371
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Claims

1. A semiconductor structure, comprising:

a p-type field-effect-transistor (PFET) channel formed in a substrate;

an n-type field-effect-transistor (nFET) channel formed in the substrate;

a shallow trench isolation structure formed in the substrate;

a first layer of material on and in physical contact with an Si layer of the substrate in the pFET channel having a lattice constant different than a lattice constant of the Si layer of the substrate;

a second layer of material on and in physical contact with the Si layer of the substrate in the nFET channel having a lattice constant different than the lattice constant of the Si layer of the substrate; and

an epitaxial semiconductor layer formed on and in physical contact with the first layer of material in the pFET channel and on and in physical contact with the second layer of material in the nFET channel, the epitaxial semiconductor layer having substantially a same lattice constant as the lattice constant of the Si layer of the substrate thus creating a desired stress component within the pFET channel and the nFET channel.

2. The structure of claim 1, wherein the first layer of material is Si:

C and the second layer of material is SiGe.

3. The structure of claim 1, wherein the first layer of material and the second layer of material is SiGe creating a stress level of greater than approximately 3 GPa in the pFET channel.

4. The structure of claim 1, wherein:

the first layer of material creates a compressive stress within the epitaxial semiconductor layer within the pFET channel; and

the second layer of material creates a tensile stress within the epitaxial semiconductor layer within the nFET channel.