Methods and apparatus for packaging integrated circuit devices

• US 7,495,341 B2
• Filed: 01/30/2007
• Issued: 02/24/2009
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Oganesian, Vage, Aksenton, Julia, Zilber, Gil
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US11/699,852
• Publication Number:
  US 20070138498A1
• Time in Patent Office: 756 Days
• Field of Search: 257/778
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14632 : Wafer-level processed structures
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 : Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 33/385 : the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.

Claims

1. An integrally packaged optronic integrated circuit device comprising:

an integrated circuit die comprising;

a substrate having first and second generally planar surfaces and edge surfaces extending away from said first or said second generally planar surface;

optronic semiconductor circuitry between said first and second generally planar surfaces;

at least one packaging layer overlying said semiconductor circuitry and said first generally planar surface; and

first and second electrical conductors overlying said second generally planar surface, said first and second electrical conductors being connected to said circuitry by first and second pads on said first generally planar surface wherein the first and second pads comprise projecting portions extending beyond one of said edge surfaces, said electrical conductors contacting said projecting portions of said pads.

3. An integrally packaged integrated circuit device according to claim 1 or claim 2, wherein said at least one packaging layer is formed of at least one of glass, quartz and sapphire.

4. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising an insulation layer formed over said second generally planar surface and said edge surfaces and underlying at least one of said electrical conductors.

5. An integrally packaged optronic integrated circuit device according to claim 4, wherein said insulation layer comprises a mechanically conforming layer.

6. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, wherein said electrical conductors are connected to said pads via portions of said electrical conductors which extend generally parallel to and in touching electrical engagement with planar surfaces of said projecting portions of said pads.

7. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, wherein said at least one packaging layer is adhered to said first generally planar surface by a bonding layer.

8. An integrally packaged optronic integrated circuit device according to claim 7, wherein said bonding layer has spectral filter functionality.

9. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising at least one spectral filter associated with at least a portion of a radiation transparent protective surface of said packaged optronic integrated surface device.

10. An integrally packaged optronic integrated circuit device according to claim 9, wherein said radiation transparent protective surface comprises at least one of a top surface and an edge surface.

11. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising color array filters.

12. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising at least one lens integrally formed on a transparent protective surface thereof.

13. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, wherein said at least one packaging layer comprises at least one lens.

14. An integrally packaged optronic integrated circuit device according to claim 12, wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

15. An integrally packaged optronic integrated circuit device according to claim 13, wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

16. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising light coupling bumps formed on a transparent protective surface thereof.

17. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising a waveguide and other optical components formed on a transparent protective surface thereof.

18. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising an optical grating formed onto a transparent protective surface thereof.

19. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising a polarizer integrated therewith.

20. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, further comprising a trench formed between different elements on said integrated circuit die.

21. An integrally packaged optronic integrated circuit device according to claim 1 or claim 2, wherein said substrate and said at least one packaging layer define at least one gap therebetween.

2. An integrally packaged optronic integrated circuit device comprising:

an integrated circuit die comprising;

a substrate having first and second generally planar surfaces and edge surfaces extending away from said first or said second generally planar surfaces, and optronic semiconductor circuitry between said first and second generally planar surfaces;

at least one packaging layer overlying said semiconductor circuitry and said first generally planar surface; and

first and second electrical conductors overlying one of said edge surfaces, said first and second electrical conductors being connected to said circuitry by first and second pads on said first generally planar surface, wherein the first and second pads comprise projecting portions extending beyond said one of said edge surfaces, said electrical conductors contacting said projecting portions of said pads.

22. An integrally packaged integrated circuit device comprising:

an integrated circuit die comprising;

a substrate having first and second generally planar surfaces and edge surfaces extending away from said first or said second generally planar surfaces, and semiconductor circuitry between said first and second generally planar surfaces;

at least one packaging layer overlying said semiconductor circuitry and said first generally planar surface; and

first and second electrical conductors overlying said second generally planar surface, said first and second electrical conductors being connected to said circuitry by first and second pads on said first generally planar surface, wherein the first and second pads comprise projecting portions extending beyond one of said edge surfaces, said electrical conductors contacting said projecting portions of said pads.

23. An integrally packaged integrated circuit device comprising:

an integrated circuit die comprising;

a substrate having first and second generally planar surfaces and edge surfaces extending away from said first or said second generally planar surfaces, and semiconductor circuitry between said first and second generally planar surfaces;

at least one packaging layer overlying said semiconductor circuitry and said first generally planar surface; and

first and second electrical conductors overlying one of said edge surfaces, said first and second electrical conductors being connected to said circuitry by first and second pads on said first generally planar surface, wherein the first and second pads comprise projecting portions extending beyond said one of said edge surfaces, said electrical conductors contacting said projecting portions of said pads.