Method of wafer-level packaging using low-aspect ratio through-wafer holes

• US 7,495,462 B2
• Filed: 08/16/2006
• Issued: 02/24/2009
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Memsic Semiconductor (Wuxi) Co., Ltd. (MZ Investment Holdings Ltd.)
• Original Assignee: Memsic Incorporated (MZ Investment Holdings Ltd.)
• Inventors: Zhao, Yang, Hua, Yaping, Li, Zongya
• Primary Examiner(s): Hollington; Jermele M
• Application Number:
  US11/505,046
• Publication Number:
  US 20060273430A1
• Time in Patent Office: 923 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/04 : characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/163 : Connection portion, e.g. seal
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

Claims

1. A method of manufacturing wafer-level packages for integrated circuits, the wafer-level packages comprising a base wafer that is fixedly attached to and in operational association with a cap wafer having a through-wafer electrical interconnection, the method comprising:

providing cavities having low-aspect ratio side-walls on both a front surface and a back surface of a polished semiconductor substrate;

providing an interconnection via between adjacent front surface cavities using a cavity disposed on the back surface;

applying a highly-electrically conductive metal/solder to surfaces of the interconnection via to provide through-wafer, low aspect ratio side-wall, electrical interconnections; and

fixedly attaching the cap wafer to the base wafer to form a composite wafer, wherein electrical contact points disposed on a front surface of the base wafer are electrically-coupled to the through-wafer, low aspect ratio side-wall electrical interconnections on the front surface of the cap wafer, and the through-wafer, low aspect ratio side-wall, electrical interconnections on the cap wafer are electrically-coupled to electrical contact points disposed on the rear surface of the cap wafer.

2. The method as recited in claim 1, wherein providing cavities having low-aspect ratio side-walls includes providing side-wall slopes that are no steeper than 1 vertical:

1 horizontal.

3. The method as recited in claim 1, wherein the method further includes annealing the cap wafer prior to fixedly attaching and electrically-coupling the cap wafer to the IC base wafer.

4. The method as recited in claim 1, wherein the method further includes filing the pre-cut interconnection via with a protective epoxy after fixedly attaching and electrically-coupling the cap wafer to the IC base wafer.

5. The method as recited in claim 1, wherein the method further includes singulating the composite wafer after fixedly attaching the cap wafer to the base wafer, to provide plural composite wafer dies.

6. The method as recited in claim 1, wherein the highly-electrically conductive metal/solder is applied to the interconnection via using electroplating, chemical vapor deposition or sputtering.

7. The method as recited in claim 1, wherein the highly-electrically conductive metal/solder applied includes metals for the group comprising gold, platinum or silver and the solder includes tin solder.

8. The method as recited in claim 7, wherein the through-wafer, side-wall electrical interconnections include a low aspect ratio side-wall portion in combination with a low-height, vertical or substantially vertical side-wall portion.

9. The method as recited in claim 8, wherein the low aspect ratio side-wall portion of the through-wafer, side-wall electrical interconnections is in direct communication with the rear surface of the cap wafer at a first end and with the vertical or substantially vertical side-wall portion at a second end.

10. The method as recited in claim 8, wherein the vertical or substantially vertical side-wall portion of the through-wafer hole, side-wall electrical interconnections is in direct communication with the front surface of the cap wafer at a first end and with the low aspect ratio side-wall portion at a second end.

11. The method as recited in claim 1, wherein the electrically conductive side-wall paths include a low aspect ratio side-wall portion in combination with a vertical or substantially vertical side-wall portion.

12. The method as recited in claim 11, wherein the low aspect ratio side-wall portion of the electrically conductive side-wall paths is in direct communication with the rear surface of the first semiconductor cap wafer at a first end and with the vertical or substantially vertical side-wall portion at a second end.

13. A method of wafer-level packaging integrated circuit (IC) dies, comprising:

providing an IC base wafer comprising a plurality of dies and at least one electrical contact point associated with each die;

providing a first semiconductor cap wafer;

forming electrically conductive side-wall paths having low aspect ratio portions through the first semiconductor cap wafer at positions corresponding to respective ones of the electrical contact points on the IC base wafer, such that each electrically conductive side-wall path extends from a first side of the first semiconductor cap wafer to a second side of the first semiconductor cap wafer and is insulated from at least a portion of the first semiconductor cap wafer; and

before singulating the dies from the IC base wafer, attaching the first semiconductor cap wafer to the IC base wafer to form a composite wafer, such that the ends of the conductive paths on the first side of the first semiconductor cap wafer are electrically-coupled to the respective electrical contact points on the IC base wafer.

14. The method as recited in claim 13, wherein the low-aspect ratio side-wall portions are formed having side-wall slopes that are no steeper than 1 horizontal:

1 vertical.

15. The method as recited in claim 13, wherein the method further includes annealing the first semiconductor cap wafer prior to fixedly attaching and electrically-coupling the said first semiconductor cap wafer to the IC base wafer.

16. The method as recited in claim 13, wherein the method further includes filing any openings in the side-wall paths with a protective epoxy after fixedly attaching and electrically-coupling the first semiconductor cap wafer to the IC base wafer;

and precutting the cap wafer.

17. The method as recited in claim 13, wherein the method further includes singulating the composite wafer after attaching the first semiconductor cap wafer to the base wafer, to provide plural composite wafer dies.

18. The method as recited in claim 13, wherein the electrically conductive side-wall paths are formed using highly-electrically conductive metal/solder that is applied using electroplating, chemical vapor deposition or sputtering.

19. The method as recited in claim 13, wherein the electrically conductive side-wall paths are formed using highly-electrically conductive metal/solder applied that includes metals for the group comprising gold, platinum or silver and the solder includes tin solder.