Non-volatile look-up table for an FPGA

• US 7,495,473 B2
• Filed: 09/20/2007
• Issued: 02/24/2009
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Greene, Jonathan, McCollum, John, Bakker, Gregory
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US11/858,330
• Publication Number:
  US 20080007292A1
• Time in Patent Office: 523 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2^x=n as is known in the art. The output of the multiplexer is coupled to V_cc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Claims

1. A non-volatile-memory-transistor based lookup table for an FPGA including:

a multiplexer having x address inputs, 2^x data inputs, and an output;

a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including;

a first non-volatile n-channel MOS transistor having a drain coupled to a power supply potential, a source coupled to the data input of the multiplexer, a floating gate, and a control gate,

a second non-volatile n-channel MOS transistor having a drain coupled to the data input of the multiplexer, a source coupled to ground, a floating gate, and a control gate, and

a sense amplifier coupled to the output of the multiplexer.

2. The non-volatile-memory-transistor based lookup table of claim 1 wherein the multiplexer has four address inputs and sixteen data inputs.

3. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory cell includes a floating gate transistor.

4. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory cell includes a nano-crystal transistor.

5. The non-volatile-memory-transistor based lookup table of claim 1 wherein each non-volatile memory cell includes a SONOS transistor.