Drive circuit

• US 7,495,475 B2
• Filed: 08/17/2007
• Issued: 02/24/2009
• Est. Priority Date: 08/24/2006
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Toshio
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/840,687
• Publication Number:
  US 20080048722A1
• Time in Patent Office: 557 Days
• Field of Search: None
• US Class Current: 326/83
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A drive circuit includes a load circuit, first and second series circuits, a bias circuit, and first and second voltage applying units. The load circuit is arranged between first and second nodes. The first series circuit is arranged between a first power supply node for supply of a first voltage and a second power supply node for supply of a second voltage. The first series circuit includes a first first-type transistor and a first second-type transistor connected in series with the first node therebetween. The second series circuit includes a second first-type transistor and a second second-type transistor connected in series with the second node therebetween. The bias circuit generates a first bias voltage to bias the first and second first-type transistors and generates a second bias voltage to bias the first and second second-type transistors. The first and second voltage applying units each include a plurality of switches.

Claims

1. A drive circuit, comprising:

a load circuit arranged between a first node and a second node;

a first series circuit arranged between a first power supply node for supply of a first voltage and a second power supply node for supply of a second voltage, the first series circuit including a first first-type transistor and a first second-type transistor connected in series with the first node therebetween;

a second series circuit including a second first-type transistor and a second second-type transistor connected in series with the second node therebetween;

a bias circuit that generates a first bias voltage to bias the first and second first-type transistors and generates a second bias voltage to bias the first and second second-type transistors;

first voltage applying means for, in a first mode, applying the first bias voltage to the first first-type transistor, applying the first voltage to the second first-type transistor, applying the second bias voltage to the second second-type transistor, and applying the second voltage to the first second-type transistor, the first voltage applying means including a plurality of switches;

second voltage applying means for, in a second mode, applying the first bias voltage to the second first-type transistor, applying the first voltage to the first first-type transistor, applying the second bias voltage to the first second-type transistor, and applying the second voltage to the second second-type transistor, the second voltage applying means including a plurality of switches, wherein

the combination of the first first-type transistor and the second second-type transistor or the combination of the second first-type transistor and the first second-type transistor cooperates with the bias circuit in functioning as the combination of current sources for the load circuit, and

the switches in the first voltage applying means and the switches in the second voltage applying means include;

a first switch and a second switch connected in parallel to apply the first voltage to the first and second first-type transistors in a complementary manner,

a third switch and a fourth switch connected in parallel to apply the first bias voltage to the first and second first-type transistors in a complementary manner,

a fifth switch and a sixth switch connected in parallel to apply the second bias voltage to the first and second second-type transistors in a complementary manner, and

a seventh switch and an eighth switch connected in parallel to apply the second voltage to the first and second second-type transistors in a complementary manner;

a voltage detection circuit that detects a voltage between the first and second nodes; and

a first differential operational amplifier circuit having a first input terminal and a second input terminal, the first input terminal being supplied with a reference voltage, the second input terminal being supplied with the voltage detected by the voltage detection circuit, wherein

the bias circuit includes

a series circuit arranged between the first and second power supply nodes, the series circuit including a bias current source and a diode, and

the first differential operational amplifier circuit, an output terminal of the first differential operational amplifier circuit is connected to a node between the third and fourth switches, and one terminal of the bias current source is connected to a node between the fifth and sixth switches.

3. The circuit according to claim 1, further comprising:

a precharge bias circuit that generates a first precharge bias voltage approximate to the threshold voltages of the first and second first-type transistors and a second precharge bias voltage approximate to the threshold voltages of the first and second second-type transistors, wherein

in the first mode, the first voltage applying means applies the first bias voltage to the first first-type transistor, applies the second bias voltage to the second second-type transistor, applies the first precharge bias voltage to the second first-type transistor, and applies the second precharge bias voltage to the first second-type transistor, and

in the second mode, the second voltage applying means applies the first bias voltage to the second first-type transistor, applies the second bias voltage to the first second-type transistor, applies the first precharge bias voltage to the first first-type transistor, and applies the second precharge bias voltage to the second second-type transistor.

2. A drive circuit comprising:

a load circuit arranged between a first node and a second node;

a first series circuit arranged between a first power supply node for supply of a first voltage and a second power supply node for supply of a second voltage, the first series circuit including a first first-type transistor and a first second-type transistor connected in series with the first node therebetween;

a second series circuit including a second first-type transistor and a second second-type transistor connected in series with the second node therebetween;

a bias circuit that generates a first bias voltage to bias the first and second first-type transistors and generates a second bias voltage to bias the first and second second-type transistors;

first voltage applying means for, in a first mode, applying the first bias voltage to the first first-type transistor, applying the first voltage to the second first-type transistor, applying the second bias voltage to the second second-type transistor, and applying the second voltage to the first second-type transistor, the first voltage applying means including a plurality of switches;

second voltage applying means for, in a second mode, applying the first bias voltage to the second first-type transistor, applying the first voltage to the first first-type transistor, applying the second bias voltage to the first second-type transistor, and applying the second voltage to the second second-type transistor, the second voltage applying means including a plurality of switches, wherein

the combination of the first first-type transistor and the second second-type transistor or the combination of the second first-type transistor and the first second-type transistor cooperates with the bias circuit in functioning as the combination of current sources for the load circuit, and

the switches in the first voltage applying means and the switches in the second voltage applying means include;

a first switch and a second switch connected in parallel to apply the first voltage to the first and second first-type transistors in a complementary manner,

a third switch and a fourth switch connected in parallel to apply the first bias voltage to the first and second first-type transistors in a complementary manner,

a fifth switch and a sixth switch connected in parallel to apply the second bias voltage to the first and second second-type transistors in a complementary manner, and

a seventh switch and an eighth switch connected in parallel to apply the second voltage to the first and second second-type transistors in a complementary manner;

a voltage detection circuit that detects a voltage between the first and second nodes;

a first differential operational amplifier circuit having a first input terminal and a second input terminal, the first input terminal being supplied with a reference voltage, the second input terminal being supplied with the voltage detected by the voltage detection circuit;

a series circuit arranged between the first and second power supply nodes, the series circuit including a bias current source and a transistor;

a second differential operational amplifier circuit having a first input terminal and a second input terminal, the first input terminal being connected to a node between the bias current source and the transistor; and

a ninth switch and a tenth switch connected in parallel, the ninth and tenth switches being turned on and off in a complementary manner, the ninth switch being arranged between one terminal of the voltage detection circuit and the second input terminal of the second differential operational amplifier circuit, the tenth switch being arranged between the other terminal of the voltage detection circuit and the second input terminal of the second differential operational amplifier circuit, wherein

the bias circuit includes

a series circuit including the bias current source and the transistor,

the first differential operational amplifier circuit,

the ninth switch,

the tenth switch, and

the second differential operational amplifier circuit;

an output terminal of the first differential operational amplifier circuit is connected to a node between the third and fourth switches, and

an output terminal of the second differential operational amplifier circuit is connected to a node between the fifth and sixth switches and is connected to a control terminal of the transistor.