Semiconductor memory device, and method of controlling the same

• US 7,495,986 B2
• Filed: 07/27/2005
• Issued: 02/24/2009
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Microelectronics America Incorporated (Fujitsu Limited)
• Inventors: Fujioka, Shinya, Sato, Kotoku, Nishimura, Koichi, Kawakubo, Tomohiro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/189,858
• Publication Number:
  US 20050262369A1
• Time in Patent Office: 1,308 Days
• Field of Search: 365/222, 365/226, 365/227, 365/228, 365/229, 327/544
• US Class Current: 365/222
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1. A system comprising:

a memory including dynamic memory cells, an internal voltage generator generating an internal voltage to be supplied to an internal voltage line, and a power supplying circuit supplying a power supply voltage as said internal voltage, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by stopping the operation of the internal voltage generator, by supplying said power supply voltage as said internal voltage by operating said power supplying circuit, and by prohibiting refresh operations, and an idle mode that operates said internal voltage generator, stops the operation of said power supplying circuit, and can perform the refresh operations, and

a memory controller outputting a command signal to the memory during the idle mode, thereby entering the memory into the low power consumption mode,

wherein said memory has a low power entry circuit to control the operations of said internal voltage generator and said power supplying circuit, and to switch between the low power consumption mode and the idle mode in response to the command signal.

2. The system according to claim 1, wherein the command signal comprises a combination of a plurality of control signals.

3. The system according to claim 1, wherein the command signal is a dedicated control signal.

4. The system according to claim 3, wherein the memory has a dedicated external terminal for receiving the dedicated control signal.

5. The system according to claim 4, wherein the memory maintains the low power consumption mode while the dedicated control signal keeps a first voltage.

6. The system according to claim 5, wherein the memory exits the low power consumption mode in response to a voltage transition from the first voltage of the dedicated control signal.

7. The system according to claim 1, wherein:

said internal voltage generator generates a voltage lower than an external power supply voltage as said internal voltage, and

said power supply voltage is the external power voltage.

8. The system according to claim 1, wherein:

said internal voltage generator generates a booster voltage higher than an external power supply voltage as said internal voltage, and

said power supply voltage is the external power voltage.

9. The system according to claim 1, wherein:

said internal voltage generator respectively generates a voltage lower than an external power supply voltage as said internal voltage and a booster voltage higher than the external power supply voltage as another internal voltage, and

said power supplying circuit supplies a power supply voltage common for both internal voltages during said low power consumption mode.

10. The system according to claim 1, wherein:

said internal voltage generator generates a negative voltage as said internal voltage, and

said power supply voltage is a ground voltage.

11. The system according to claim 1, comprising a bit line connected to said dynamic memory cells, wherein:

said internal voltage generator generates a precharge voltage for the bit line as said internal voltage, and

said power supply voltage is a ground voltage.

12. The system according to claim 1, comprising a bit line connected to said dynamic memory cells, wherein:

said internal voltage generator generates a precharge voltage respectively for the bit line and a negative voltage as said internal voltage and another internal voltage, and

said power supplying circuit supplies a power supply voltage common for both internal voltages during said low power consumption mode.