Proximity communication-based off-chip cache memory architectures
First Claim
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1. A system, comprising:
- a first processor;
a first cache overlapping a first corner of the first processor;
a second cache overlapping a second corner of the first processor;
a third cache overlapping a third corner of the first processor;
a fourth cache overlapping a fourth corner of the first processor, wherein the first cache, the second cache, the third cache, and the fourth cache belong to a plurality of off-chip cache memories and are operatively connected to the first processor by proximity communication; and
a physical memory comprising a physical address space,wherein the first cache is configured to cache data for the first processor only from a first portion of the physical address space,wherein the second cache is configured to cache data for the first processor only from a second portion of the physical address space,wherein the third cache is configured to cache data for the first processor only from a third portion of the physical address space, andwherein the fourth cache is configured to cache data for the first processor only from a fourth portion of the physical address space.
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Abstract
A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a plurality of processors that are dependent on the plurality of off-chip cache memories for servicing requests for data. The plurality of off-chip cache memories are operatively connected to either one another or to one or more of the plurality of processors by proximity communication. Each of the plurality of off-chip cache memories may cache certain portions of the physical address space.
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Citations
12 Claims
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1. A system, comprising:
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a first processor; a first cache overlapping a first corner of the first processor; a second cache overlapping a second corner of the first processor; a third cache overlapping a third corner of the first processor; a fourth cache overlapping a fourth corner of the first processor, wherein the first cache, the second cache, the third cache, and the fourth cache belong to a plurality of off-chip cache memories and are operatively connected to the first processor by proximity communication; and a physical memory comprising a physical address space, wherein the first cache is configured to cache data for the first processor only from a first portion of the physical address space, wherein the second cache is configured to cache data for the first processor only from a second portion of the physical address space, wherein the third cache is configured to cache data for the first processor only from a third portion of the physical address space, and wherein the fourth cache is configured to cache data for the first processor only from a fourth portion of the physical address space. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system, comprising:
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a first processor; a proximity interconnect module operatively connected to main memory, wherein the main memory comprises a physical address space; a first cache overlapping a first corner of the first processor; a second cache overlapping a second corner of the first processor; a third cache overlapping a third corner of the first processor; and a fourth cache overlapping a fourth corner of the first processor, wherein the first cache, the second cache, the third cache, and the fourth cache belong to a plurality of off-chip cache memories disposed on the proximity interconnect module, wherein the first cache is configured to cache data for the first processor only from a first portion of the physical address space, wherein the second cache is configured to cache data for the first processor only from a second portion of the physical address space, wherein the third cache is configured to cache data for the first processor only from a third portion of the physical address space, and wherein the fourth cache is configured to cache data for the first processor only from a fourth portion of the physical address space. - View Dependent Claims (9, 10, 11, 12)
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Specification