System and method of execution of register pointer instructions ahead of instruction issues

• US 7,496,733 B2
• Filed: 10/26/2007
• Issued: 02/24/2009
• Est. Priority Date: 04/21/2004
• Status: Expired due to Term

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Altman, Erik, Wellman, John-David, Gschwind, Michael Karl, Rivers, Jude A., Zyuban, Victor, Sathaye, Sumedh Wasudeo
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Fennema; Robert E
• Application Number:
  US11/924,977
• Publication Number:
  US 20080052495A1
• Time in Patent Office: 487 Days
• Field of Search: 712/216
• US Class Current: 712/216
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

Claims

1. A pipeline, comprising:

a plurality of operational stages, the stages including;

a pointer register stage which stores pointer information and updates;

a pointer dependency checking stage located upstream of the pointer register stage, which determines if instruction pointer dependencies exist and stalls an instruction if necessary to resolve inter-instruction dependencies in the pointer register stage;

a dependence checking stage located downstream of the pointer register stage and configured to perform checking on instructions and stall an instruction if necessary to resolve inter-instruction dependencies in an instruction register file; and

at least one pointer functional unit configured to provide pointer information updates directly to the pointer register stage.

2. The pipeline as recited in claim 1, further comprising an issue stage located downstream from the dependence checking stage.

3. The pipeline as recited in claim 1, wherein the instruction register file is configured to store instruction information and updates.

4. The pipeline as recited in claim 1, wherein the at least one pointer functional unit provides pointer information updates directly to an input of the at least one pointer functional unit as a pointer bypass.

5. The pipeline as recited in claim 1, further comprising at least one instruction functional unit configured to provide information updates directly to the instruction register file and/or directly to an input of the at least one instruction functional unit as an instruction bypass such that instruction update information is processed and updated and wherein instructions updating the instruction register file and instructions updating the pointer register stage are simultaneously processed to track and keep current pointer and dependency updates between instructions.

6. The pipeline as recited in claim 1, wherein the at least one pointer functional unit is located between the pointer register stage and the dependence checking stage such that inter-instruction dependency is checked after the at least one pointer functional unit or in parallel with pointer execution.

7. The pipeline as recited in claim 6, further comprising a path for making pointer updates available to the pointer register stage before the instruction reaches a write back stage of the pipeline.

8. The pipeline as recited in claim 7, wherein the path includes a normal pointer update path which returns pointer information from the at least one pointer functional unit.

9. The pipeline as recited in claim 1, wherein the pointer bypass makes pointer updates available to immediately following instructions before a pointer update is written into the pointer register stage.

10. The pipeline as recited in claim 1, further comprising a pointer reorder buffer coupled to the pointer register stage to maintain a precise state of pointers.

11. The pipeline as recited in claim 10, further comprising a precise pointer file for storing the precise state of the pointer reorder buffer.

12. The pipeline as recited in claim 11, further comprising an interrupt recovery path which keeps the pointer register stage up to date with reordering or recovery information from the precise pointer file.

13. The pipeline as recited in claim 1, further comprising a combined pointer reorder buffer/issue stage coupled to the dependence checking stage to issue instructions and maintain a precise state/order of pointers.

14. The pipeline as recited in claim 13, wherein the combined pointer reorder buffer/issue stage includes a table with a plurality of fields to keep identifiers of all pointers that are updated by an instruction, and new values of the updated pointers.

15. The pipeline as recited in claim 14, further comprising a precise pointer file for storing the precise state of the combined pointer reorder buffer/issue stage.

16. The pipeline as recited in claim 15, further comprising an interrupt recovery path, which restores the pointer register stage to the precise state from the precise pointer file.

17. A method for updating pointers ahead of an instruction, comprising the steps of:

providing a plurality of operational stages, including a pointer register stage which stores pointer information and updates, a pointer dependence checking stage located upstream of the pointer register stage, which determines if instruction dependencies exist and stalls an instruction if necessary to resolve inter-instruction dependencies in the pointer register stage, a dependence checking stage located downstream of the pointer register file and configured to perform checking on instructions and stall an instruction if necessary to resolve inter-instruction dependencies in an instruction register file configured to store instruction information and updates, and at east one pointer functional unit providing pointer information updates directly to the pointer register stage; and

processing instruction dependency information and pointer information to update the pointer register stage so that instructions updating the instruction register file and instructions updating the pointer register stage are simultaneously processed to track and keep current pointer and dependency updates between instructions.

18. The method as recited in claim 17, wherein the at least one pointer functional unit provides pointer information updates directly to an input of the at least one pointer functional unit as a pointer bypass.

19. The method as recited in claim 17, wherein at least one instruction functional unit provides information updates directly to the instruction register file and/or directly to an input of the at least one instruction functional unit as an instruction bypass.

20. The method as recited in claim 17, further comprising providing pointer updates to the pointer register stage via an early pointer update path by providing the at least one pointer functional stage between the pointer register stage and the dependence checking stage.