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Data encryption interface for reducing encrypt latency impact on standard traffic

  • US 7,496,753 B2
  • Filed: 09/02/2004
  • Issued: 02/24/2009
  • Est. Priority Date: 09/02/2004
  • Status: Expired due to Fees
First Claim
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1. A system on a chip (SOC), comprising:

  • one or more processor cores;

    an encryption engine;

    one or more write buffers; and

    data flow control circuitry configured to route secure data involved in a first store instruction to the one or more write buffers through a first data path through the encryption engine, and to route non-secure data involved in a second store instruction issued subsequent to the first store instruction to the one or more write buffers through a second data path bypassing the encryption engine, wherein the non-secure data arrives at the one or more write buffers prior to the secure data.

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