Data encryption interface for reducing encrypt latency impact on standard traffic

• US 7,496,753 B2
• Filed: 09/02/2004
• Issued: 02/24/2009
• Est. Priority Date: 09/02/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuesel, Jamie R., Beukema, Bruce L., Shearer, Robert A.
• Primary Examiner(s): Peeso; Thomas R
• Application Number:
  US10/932,943
• Publication Number:
  US 20060047975A1
• Time in Patent Office: 1,636 Days
• Field of Search: 713/165, 713/166, 713/167, 713/193
• US Class Current: 713/165
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Abstract

Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data.

Claims

1. A system on a chip (SOC), comprising:

one or more processor cores;

an encryption engine;

one or more write buffers; and

data flow control circuitry configured to route secure data involved in a first store instruction to the one or more write buffers through a first data path through the encryption engine, and to route non-secure data involved in a second store instruction issued subsequent to the first store instruction to the one or more write buffers through a second data path bypassing the encryption engine, wherein the non-secure data arrives at the one or more write buffers prior to the secure data.

2. The SOC of claim 1, wherein the data flow control circuitry is configured to determine data contained in a store instruction is secure based on an address contained in the store instruction.

3. The SOC of claim 1, further comprising a hold buffer for receiving secure data, in encrypted form, from the encryption engine.

4. The SOC of claim 3, wherein the data flow control circuitry comprises one or more multiplexors to selectively route secure data, in encrypted form, from the encryption engine to the one or more write buffers or the hold buffer, based on availability of the one or more write buffers.

5. The SOC of claim 3, wherein the data flow control circuitry comprises one or more multiplexors to selectively route non-secure data to the hold buffer, based on availability of the one or more write buffers.