Method and system for generating clocks for standby mode operation in a mobile communication device
First Claim
1. A method for reducing power while in standby mode, the method comprising:
- monitoring for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode, wherein said low power standby clock signal is generated by an off-chip clock source; and
upon receiving said at least one event, enabling one or both of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal, wherein said first clock signal and said second clock signal are generated by a clock source on said chip.
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Accused Products
Abstract
Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.
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Citations
27 Claims
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1. A method for reducing power while in standby mode, the method comprising:
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monitoring for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode, wherein said low power standby clock signal is generated by an off-chip clock source; and upon receiving said at least one event, enabling one or both of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal, wherein said first clock signal and said second clock signal are generated by a clock source on said chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A machine-readable storage having stored thereon, a computer program having at least one code section for reducing power while in standby mode, the at least one code section executable by a machine for causing the machine to perform steps comprising:
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monitoring for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode, wherein said low power standby clock signal is generated by an off-chip clock source; and upon receiving said at least one event, enabling one or both of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal, wherein said first clock signal and said second clock signal are generated by a clock source on said chip. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A system for reducing power while in standby mode, the system comprising:
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at least one processor that monitors for an occurrence of at least one event requiring a transition out of the standby mode while utilizing a low power standby clock signal while in the standby mode, wherein said low power standby clock signal is generated by an off-chip clock source; and upon receiving said at least one event, said at least one processor enables one or both of a first clock signal and a second clock signal that consumes more power than said low power standby clock signal, said low power standby clock signal having a lower frequency and lower accuracy than said first clock signal and said second clock signal, wherein said first clock signal and said second clock signal are generated by a clock source on said chip. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification