Timing signal generating circuit with a master circuit and slave circuits

• US 7,496,781 B2
• Filed: 10/24/2002
• Issued: 02/24/2009
• Est. Priority Date: 06/12/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka, Wakayama, Shigetoshi, Yamaguchi, Hisakatsu, Ogawa, Junji, Gotoh, Kohtaroh
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Bae; Ji H
• Application Number:
  US10/278,800
• Publication Number:
  US 20030042957A1
• Time in Patent Office: 2,315 Days
• Field of Search: 713/600, 713/503, 327/156
• US Class Current: 713/600
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Claims

1. A timing signal generating circuit comprising:

a master circuit for generating an internal signal having the same cycle or the same phase as that of an input reference signal on the basis of a control signal generated by feedback control, said master circuit comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit, and a first variable delay line for outputting said internal signal by controlling a delay amount for said reference signal in accordance with said control signal, said control signal generating circuit including a charge pump circuit for controlling an output voltage level in accordance with an up signal and a down signal from said comparator circuit;

at least two slave circuits each for generating a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and said control signal from said master circuit, each of said at least two slave circuits comprising a second variable delay line for outputting said timing signal by delaying said internal signal, and a phase interpolator for accepting input signals of different phases and for outputting a finer timing signal of an intermediate phase, without comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, and a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit; and

at least two receiver circuits, each receiving the finer timing signal output from corresponding one of said slave circuits, latching a receiving signal and detecting a level of the receiving signal based on the finer timing signal, and feedback controlling a delay value of the input signals to said phase interpolator.

2. A timing signal generating circuit as claimed in claim 1, wherein said master circuit contains a circuit corresponding to one of said at least two slave circuits so that said master circuit also outputs a timing signal by itself.

3. A timing signal generating circuit as claimed in claim 1, wherein said master circuit is a DLL circuit which comprises a coarse delay control block for performing coarse delay control and a fine delay control block for performing fine delay control, and each of said at least two slave circuits contains a circuit corresponding to said fine delay control block.

4. A timing signal generating circuit as claimed in claim 3, wherein said coarse delay control block takes taps off said delay line consisting of a plurality of delay units, and performs coarse delay control by selecting an output of each of said taps, while said fine delay control block receives a signal for controlling the DLL circuit in said coarse delay control block and a signal subjected to said coarse delay control in said coarse delay control block, and performs fine delay control through an interpolator by using said coarse delay control signal.

5. A timing signal generating circuit as claimed in claim 1, wherein said control signal generating circuit includes an up-down counter for counting an up signal and a down signal from said comparator circuit and a D/A converter for performing digital-to-analog conversion on an output of said up-down counter.

6. A timing signal generating circuit as claimed in claim 1, wherein said at least two slave circuits each include an amplifier circuit whose response speed varies in accordance with a signal from said master circuit, and generates a signal of sinusoidal waveform as said timing signal.

7. A timing signal generating circuit as claimed in claim 1, wherein each of said at least two slave circuits are used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and said timing signal generating circuit includes timing signal adjusting means, provided common to each of said at least two slave circuits, for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.

8. A timing signal generating circuit as claimed in claim 7, wherein said timing signal adjusting means includes selecting means for selecting an input or output signal of a circuit controlled by said timing signal from each of the at least two slave circuits, and timing signal generating means for controlling output timing of said timing signal by detecting the level of said input or output signal of said circuit selected by said selecting means.

9. A timing signal generating circuit as claimed in claim 1, wherein each of said at least two slave circuits is used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and each of said at least two slave circuits includes timing signal adjusting means for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.

10. A semiconductor integrated circuit device employing a timing signal generating circuit comprising a master circuit, at least two slave circuits, and at least two receiver circuits, said master circuit and said slave circuit being formed on the same semiconductor chip used for said semiconductor integrated circuit device, wherein:

said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal on the basis of a control signal generated by feedback control; and

each of said slave circuits generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and said control signal from said master circuit,

wherein said master circuit comprises;

a comparator circuit for comparing the cycle of phase of said internal signal with that of said reference signal;

a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit, said control signal generating circuit including a charge pump circuit for controlling an output voltage level in accordance with an up signal and a down signal from said comparator circuit; and

a first variable delay line for outputting said internal signal by controlling a delay amount for said reference signal in accordance with said control signal,

wherein each of said slave circuits comprises;

a second variable delay line for outputting said timing signal by delaying said internal signal; and

a phase interpolator for accepting input signals of different phases and for outputting a finer timing signal of an intermediate phase, without comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, and a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit,

and wherein each of said receiver circuits receives the finer timing signal output from corresponding one of said slave circuits, latches a receiving signal and detects a level of the receiving signal based on the finer timing signal, and feedback controls a delay value of the input signals to said phase interpolator.

11. A semiconductor integrated circuit device as claimed in claim 10, wherein said master circuit contains a circuit corresponding to one of said at least two slave circuits so that said master circuit also outputs a timing signal by itself.

12. A semiconductor integrated circuit device as claimed in claim 10, wherein said master circuit is a DLL circuit which comprises a coarse delay control block for performing coarse delay control and a fine delay control block for performing fine delay control, and each of said at least two slave circuits contains a circuit corresponding to said fine delay control block.

13. A semiconductor integrated circuit device as claimed in claim 12, wherein said coarse delay control block takes taps off said delay line consisting of a plurality of delay units, and performs coarse delay control by selecting an output of each of said taps, while said fine delay control block receives a signal for controlling the DLL circuit in said coarse delay control block and a signal subjected to said coarse delay control in said coarse delay control block, and performs fine delay control through an interpolator by using said coarse delay control signal.

14. A semiconductor integrated circuit device as claimed in claim 10, wherein said control signal generating circuit includes an up-down counter for counting an up signal and a down signal from said comparator circuit and a D/A converter for performing digital-to-analog conversion on an output of said up-down counter.

15. A semiconductor integrated circuit device as claimed in claim 10, wherein each of said at least two slave circuits includes a variable delay line for outputting said timing signal by delaying said internal signal in accordance with said control signal from said master circuit.

16. A semiconductor integrated circuit device as claimed in claim 10, wherein each of said at least two slave circuits includes an amplifier circuit whose response speed varies in accordance with a signal from said master circuit, and generates a signal of sinusoidal waveform as said timing signal.

17. A semiconductor integrated circuit device as claimed in claim 10, wherein each of said at least two slave circuits is used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and said timing signal generating circuit includes timing signal adjusting means, provided common to each of said at least two slave circuits, for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.

18. A semiconductor integrated circuit device as claimed in claim 17, wherein said timing signal adjusting means includes selecting means for selecting an input or output signal of a circuit controlled by said timing signal from each of said at least two slave circuits, and timing signal generating means for controlling output timing of said timing signal by detecting the level of said input or output signal of said circuit selected by said selecting means.

19. A semiconductor integrated circuit device as claimed in claim 10, wherein each of said at least two slave circuits is used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and each of said at least two slave circuits includes timing signal adjusting means for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.

20. A semiconductor integrated circuit system employing a timing signal generating circuit comprising a master circuit, at least two slave circuits, and at least two receiver circuits, said semiconductor integrated circuit system having a plurality of semiconductor integrated circuit devices, each of said semiconductor integrated circuit devices having said master circuit and/or said slave circuit and being formed on corresponding one semiconductor chip, wherein:

said master circuit generates an internal signal having the same cycle or the same phase as that of an input reference signal on the basis of a control signal generated by feedback control, and said master circuit is a DLL circuit which comprises a coarse delay control block for performing coarse delay control and a fine delay control block for performing fine delay control, said master circuit comprising a comparator circuit for comparing the cycle or phase of said internal signal with that of said reference signal, a control signal generating circuit for varying said control signal in accordance with an output of said comparator circuit, and a variable delay line for outputting said internal signal by controlling a delay amount for said reference signal in accordance with said control signal, said control signal generating circuit including a charge pump circuit for controlling an output voltage level in accordance with an up signal and down signal from said comparator circuit;

each of said at least two slave circuits includes a phase interpolator for accepting input signals of different phases and for outputting a finer timing signal of an intermediate phase, and generates a timing signal having prescribed timing relative to said reference signal by receiving said internal signal and said control signal from said master circuit, without containing a circuit corresponding to said coarse delay control block for performing course delay control; and

each of said at least two receiver circuits receives the finer timing signal output from corresponding one of said slave circuits, latches a receiving signal and detects a level of the receiving signal based on the finer timing signal, and feedback controls a delay value of the input signals to said phase interpolator.

21. A semiconductor integrated circuit system as claimed in claim 20, wherein said master circuit contains a circuit corresponding to one of said at least two slave circuits so that said master circuit also outputs a timing signal by itself.

22. A semiconductor integrated circuit system as claimed in claim 20, wherein said coarse delay control block takes taps off said delay line consisting of a plurality of delay units, and performs coarse delay control by selecting an output of each of said taps, while said fine delay control block receives a signal for controlling the DLL circuit in said coarse delay control block and a signal subjected to said coarse delay control in said coarse delay control block, and performs fine delay control through an interpolator by using said coarse delay control signal.

23. A semiconductor integrated circuit system as claimed in claim 20, wherein said control signal generating circuit includes an up-down counter for counting an up signal and a down signal from said comparator circuit and a D/A converter for performing digital-to-analog conversion on an output of said up-down counter.

24. A semiconductor integrated circuit system as claimed in claim 20, wherein each of said at least two slave circuits includes a variable delay line for outputting said timing signal by delaying said internal signal in accordance with said control signal from said master circuit.

25. A semiconductor integrated circuit system as claimed in claim 20, wherein each of said at least two slave circuits includes an amplifier circuit whose response speed varies in accordance with a signal from said master circuit, and generates a signal of sinusoidal waveform as said timing signal.

26. A semiconductor integrated circuit system as claimed in claim 20, wherein each of said at least two slave circuits is used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and said timing signal generating circuit includes timing signal adjusting means, provided common to each of said at least two slave circuits, for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.

27. A semiconductor integrated circuit system as claimed in claim 26, wherein said timing signal adjusting means includes selecting means for selecting an input or output signal of a circuit controlled by said timing signal from each of said at least two slave circuits, and timing signal generating means for controlling output timing of said timing signal by detecting the level of said input or output signal of said circuit selected by said selecting means.

28. A semiconductor integrated circuit system as claimed in claim 20, wherein each of said at least two slave circuits is used to generate a timing signal for controlling the timing of one-bit or multiple-bit input or output signals, and each of said at least two slave circuits includes timing signal adjusting means for adjusting said timing signal so as to increase the S/N ratio of a transmitted and received signal.