Concurrent optimization of physical design and operational cycle assignment

• US 7,496,879 B2
• Filed: 03/15/2005
• Issued: 02/24/2009
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US11/081,823
• Publication Number:
  US 20070245272A1
• Time in Patent Office: 1,442 Days
• Field of Search: 716/16, 716/17, 716/18, 716/7
• US Class Current: 716/138
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In some embodiments, the method concurrently optimizes the assignment of the operations to different operation cycles and different configurable circuits. In some embodiments, the optimization includes moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.

Claims

1. A method of designing an integrated circuit (“

IC”

) comprising a plurality of configurable circuits including a plurality of configurable interconnect circuits, the method comprising;

concurrently assigning each of a plurality of operations in an IC design to an operational cycle and a configurable circuit,

wherein concurrently assigning the operations comprises;

assigning a first operation to a first operational cycle and a first configurable circuit; and

after assigning the first operation to the first operational cycle and the first configurable circuit, assigning a second operation to a second operational cycle and a second configurable circuits,

wherein at least one of the concurrently assigned operations is an interconnect operation that is assigned to a configurable interconnect circuit.

2. The method of claim 1, wherein the assigning further comprises concurrently optimizing the assignment of the operations to different operational cycles and different configurable circuits.

3. The method of claim 2, wherein the optimizing comprises moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.

4. The method of claim 1, wherein the assigning further comprises swapping the operational cycles or configurable circuits to which pairs of operations are assigned.

5. The method of claim 1, wherein the IC is a sub-cycle reconfigurable IC, and the operational cycles are sub-cycles related to a clock cycle.

6. The method of claim 1, wherein assigning the first operation to the first configurable circuit comprises defining a first configuration data set for the first configurable circuit, wherein the first configuration data set is for configuring the first configurable circuit to perform the first operation.

7. The method of claim 6,

wherein the IC is a reconfigurable IC,

wherein each of the plurality of configurable circuits is for reconfiguring multiple times during multiple operational cycles,

wherein defining the first configuration data set for the first configurable circuit comprises defining the first configuration data set as the configuration data set for the first configurable circuit during a first operational cycle.

8. The method of claim 7 further comprising defining a second configuration data set for the first configurable circuit in a second operational cycle, wherein the second configuration data set is for configuring the first configurable circuit to perform a second operation during the second operational cycle.

9. The method of claim 8, wherein the plurality of configurable circuits comprises a plurality of configurable logic circuits, and at least one of the first and second operations are functions performed by a particular configurable logic circuit.

10. The method of claim 8, wherein the first configurable circuit is a configurable interconnect circuit, and the first and second operations are interconnect operations performed by the configurable interconnect circuit.

11. A method of designing a reconfigurable integrated circuit (“

IC”

) that implements an IC design that comprises a plurality of components, the reconfigurable IC comprising a plurality of reconfiguration cycles and a plurality of reconfigurable circuits including a plurality of reconfigurable logic circuits and a plurality of reconfigurable interconnect circuits, the method comprising;

a) assigning the components to reconfigurable circuits and reconfiguration cycles of the reconfigurable IC,

b) said assigning comprising concurrently optimizing the reconfigurable-circuit and reconfiguration-cycle assignments of the components, the concurrent optimization comprising specifying operations for the reconfigurable interconnect circuits to perform in the plurality of reconfiguration cycles.

12. The method of claim 11, wherein at least one of the reconfigurable circuits can have a new configuration during each reconfiguration cycle.

13. A computer readable medium that stores a computer program which when executed by at least one processor designs an integrated circuit (“

IC”

) with a plurality of configurable circuits including a plurality of configurable interconnect circuits, the computer program comprising sets of instructions for;

concurrently assigning each of a plurality of operations in an IC design to an operational cycle and a configurable circuit,

wherein the set of instructions for concurrently assigning the operations comprises a set of instructions for assigning a first operation to a first operational cycle and a first configurable circuit before assigning a second operation to a second operational cycle and a second configurable circuit,

wherein at least one of the concurrently assigned operations is an interconnect operation that is assigned to a configurable interconnect circuit.

14. The computer readable medium of claim 13, wherein the set of instructions for assigning further comprises a set of instructions for concurrently optimizing the assignment of the operations to different operational cycles and different configurable circuits.

15. The computer readable medium of claim 14, wherein the set of instructions for optimizing comprises a set of instructions for moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.

16. The computer readable medium of claim 13, wherein the set of instructions for assigning further comprises a set of instructions for swapping the operational cycles or configurable circuits to which pairs of operations are assigned.

17. The computer readable medium of claim 13, wherein the IC is a sub-cycle reconfigurable IC, and the operational cycles are sub-cycles related to a clock cycle.

18. The computer readable medium of claim 13, wherein the set of instructions for assigning the first operation to the first configurable circuit comprises a set of instructions for defining a first configuration data set for the first configurable circuit, wherein the first configuration data set is for configuring the first configurable circuit to perform the first operation.

19. The computer readable medium of claim 18,

wherein the IC is a reconfigurable IC,

wherein each of a plurality of configurable circuits is for reconfiguring multiple times during multiple operational cycles,

wherein the set of instructions for defining the first configuration data set for the first configurable circuit comprises a set of instructions for defining the first configuration data set as the configuration data set for the first configurable circuit during a first operational cycle.

20. The computer readable medium of claim 19, wherein the program further comprises a set of instructions for defining a second configuration data set for the first configurable circuit in a second operational cycle, the second configuration data set for configuring the first configurable circuit to perform a second operation during the second operational cycle.

21. A computer readable medium that stores a computer program which when executed by at least one processor designs a reconfigurable integrated circuit (“

IC”

) that implements an IC design that comprises a plurality of components, the reconfigurable IC comprising a plurality of reconfiguration cycles and a plurality of reconfigurable circuits including a plurality of reconfigurable logic circuits and a plurality of reconfigurable interconnect circuits, the computer program comprising;

a) a set of instructions for assigning the components to reconfigurable circuits and reconfiguration cycles of the reconfigurable IC,

b) said set of instructions for assigning comprising a set of instructions for concurrently optimizing the reconfigurable-circuit and reconfiguration-cycle assignments of the components, the set of instructions for concurrently optimizing comprising a set of instructions for specifying operations for the reconfigurable interconnect circuits to perform in the plurality of reconfiguration cycles.

22. The computer readable medium of claim 21, wherein at least one of the reconfigurable circuits can have a new configuration during each reconfiguration cycle.