Post passivation interconnection schemes on top of the IC chips

• US 7,498,255 B2
• Filed: 01/25/2008
• Issued: 03/03/2009
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US12/019,644
• Publication Number:
  US 20080138978A1
• Time in Patent Office: 403 Days
• Field of Search: 438614-616, 438/618, 438/622, 438/624, 438/631, 438/637, 438/638
• US Class Current: 438/618
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating a chip structure, comprising:

providing a silicon substrate, a first internal circuit in and on said silicon substrate, a second internal circuit in and on said silicon substrate, a first intra-chip driver or receiver in and on said silicon substrate, a second intra-chip driver or receiver in and on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure connects a first terminal of said first intra-chip driver or receiver to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure connects a first terminal of said second intra-chip driver or receiver to said second internal circuit, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a second terminal of said first intra-chip driver or receiver, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to a second terminal of said second intra-chip driver or receiver, and a passivation layer over said dielectric layer; and

forming a fifth interconnecting structure and a polymer layer over said passivation layer, wherein said fifth interconnecting structure is in said polymer layer, and wherein said second terminal of said first intra-chip driver or receiver is connected to said second terminal of said second intra-chip driver or receiver through, in sequence, said third interconnecting structure, said fifth interconnecting structure and said fourth interconnecting structure.

2. The method of claim 1, wherein said fifth interconnecting structure comprises a data-signal line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

3. The method of claim 1, wherein said fifth interconnecting structure comprises a logic-signal line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

4. The method of claim 1, wherein said fifth interconnecting structure comprises a clock line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

5. The method of claim 1, wherein said forming said fifth interconnecting structure comprises a copper electroplating process.

6. The method of claim 1, wherein said forming said fifth interconnecting structure comprises a gold electroplating process.

7. The method of claim 1, wherein said forming said fifth interconnecting structure comprises sputtering a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.

8. The method of claim 1, wherein said fifth interconnecting structure comprises a line of a power voltage output from a voltage regulator, wherein said line connects said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

9. The method of claim 1 further comprising providing an off-chip driver, receiver or I/O circuit in and on said silicon substrate, and a sixth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said sixth interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit, wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said first intra-chip driver or receiver through, in sequence, said sixth interconnecting structure, said fifth interconnecting structure and said third interconnecting structure, and wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said second intra-chip driver or receiver through, in sequence, said sixth interconnecting structure, said fifth interconnecting structure and said fourth interconnecting structure.

10. The method of claim 9 further comprising providing an ESD circuit in and on said silicon substrate, and a seventh interconnecting structure over said silicon substrate and in said dielectric layer, wherein said seventh interconnecting structure connects said ESD circuit to a second terminal of said off-chip driver, receiver or I/O circuit.

11. The method of claim 1, wherein said passivation layer comprises a nitride.

12. A method for fabricating a chip structure, comprising:

providing a silicon substrate, an internal circuit in and on said silicon substrate, an intra-chip driver or receiver in and on said silicon substrate, an off-chip driver, receiver or I/O circuit in and on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure connects a first terminal of said intra-chip driver or receiver to said internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said intra-chip driver or receiver, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit, and a passivation layer over said dielectric layer; and

forming a fourth interconnecting structure and a polymer layer over said passivation layer, wherein said fourth interconnecting structure is in said polymer layer, and wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said intra-chip driver or receiver through, in sequence, said third interconnecting structure, said fourth interconnecting structure and said second interconnecting structure.

13. The method of claim 12, wherein said fourth interconnecting structure comprises a data-signal line connecting said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.

14. The method of claim 12, wherein said forming said fourth interconnecting structure comprises a copper electroplating process.

15. The method of claim 12, wherein said forming said fourth interconnecting structure comprises a gold electroplating process.

16. The method of claim 12, wherein said forming said fourth interconnecting structure comprises sputtering a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.

17. The method of claim 12, wherein said fourth interconnecting structure comprises a line of a power voltage output from a voltage regulator, wherein said line connects said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.

18. The method of claim 12 further comprising providing an ESD circuit in and on said silicon substrate, and a fifth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fifth interconnecting structure connects said ESD circuit to a second terminal of said off-chip driver, receiver or I/O circuit.

19. The method of claim 12, wherein said passivation layer comprises a nitride.

20. The method of claim 12, wherein said fourth interconnecting structure comprises a clock line connecting said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.