Manufacturing method for semiconductor device, semiconductor device, and electronic apparatus

• US 7,498,661 B2
• Filed: 05/30/2006
• Issued: 03/03/2009
• Est. Priority Date: 03/25/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Matsuo, Yoshihide
• Primary Examiner(s): Wilczewski; M.
• Assistant Examiner(s): Green; Telly D
• Application Number:
  US11/442,897
• Publication Number:
  US 20060214302A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/621, 257/777, 257/678, 257/698, 257/700, 257/735
• US Class Current: 257/621
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A manufacturing method for a semiconductor device includes a hole portion formation step for forming hole portions whose entire width is substantially identical to the width of the opening portion in a part of the active surface side of the substrate on which electronic components are formed, a curved surface formation step for curving the bottom surface of the hole portion while maintaining the width of the bottom surface in the hole portions substantially identical to the width of the opening portion, a connecting terminal formation step for forming connecting terminals that serve as the external electrodes of the electronic circuits by burying metal in the hole portions, and an exposure step for exposing a part of the connecting terminals by carrying out processing on the back surface of the substrate.

Claims

1. A semiconductor device comprising:

a thinned substrate having an active surface side on which electronic circuits are formed and a back surface side opposite the active surface side; and

connecting terminals that serve as external electrodes for the electronic circuits, the connecting terminals passing through the substrate from the active surface side to the back surface side;

wherein distal ends of the connecting terminals at the back surface side of the substrate have a plurality of surface undulations which comprise one of;

a plurality of convex outward surfaces; and

a plurality of concave inward surfaces, and

wherein the connecting terminals respectively include a first part and a second part, the first part being directly connected to the electronic circuits, the second part passing through the substrate, the first part and the second part consisting of the same metal and forming a unit.

2. A semiconductor device wherein the semiconductor device according to claim 1 are stacked in plurality and the second parts of one and another of the connecting terminals are bonded together in a line.

3. A semiconductor device comprising:

a mounting substrate on which a connection part is formed; and

one or a plurality of a semiconductor device according to claim 1 are mounted on the mounting substrate;

wherein the connecting terminals are bonded together or the connecting portion and the connecting terminals are bonded together.

4. An electronic apparatus comprising the semiconductor device according to claim 1.