Fractional-N frequency synthesizer
First Claim
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1. A circuit comprising:
- a voltage-controlled oscillator comprising an output port to provide an output clock signal, the circuit to provide a first feedback signal derived from the output clock signal;
a divider circuit to provide a second feedback signal derived from the output clock signal divided by N+1 with a probability α and
divided by N with a probability 1−
α
, where N is an integer; and
a phase frequency detector to provide a first logic signal that is asserted at a rising edge of the reference signal, and to provide a second logic signal that is asserted at a rising edge of the second feedback signal, the phase frequency detector to sample the second logic signal at a rising edge of the first feedback signal to generate a third logic signal, where the third logic signal is sampled at a rising edge of the first feedback signal to generate a reset signal, where the first, second, and third signals are de-asserted after both the first and reset signals are asserted.
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Abstract
A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-lockup loop fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.
55 Citations
16 Claims
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1. A circuit comprising:
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a voltage-controlled oscillator comprising an output port to provide an output clock signal, the circuit to provide a first feedback signal derived from the output clock signal; a divider circuit to provide a second feedback signal derived from the output clock signal divided by N+1 with a probability α and
divided by N with a probability 1−
α
, where N is an integer; anda phase frequency detector to provide a first logic signal that is asserted at a rising edge of the reference signal, and to provide a second logic signal that is asserted at a rising edge of the second feedback signal, the phase frequency detector to sample the second logic signal at a rising edge of the first feedback signal to generate a third logic signal, where the third logic signal is sampled at a rising edge of the first feedback signal to generate a reset signal, where the first, second, and third signals are de-asserted after both the first and reset signals are asserted. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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a loop filter; a charge pump responsive to a first logic signal, a second logic signal, a third logic signal, and a signal indicative of a parameter ε
, where 0≦
ε
≦
1, to source to the loop, a first amount charge, a second amount of charge, and a third amount of charge only if the first, the second, and third logic signals are asserted, respectively, wherein the sum of the first, second, and third amounts of charge is substantially zero regardless of the parameter ε
;a voltage-controlled oscillator coupled to the loop filter to provide an output clock signal; and a phase frequency detector responsive to a reference signal, a first feedback signal derived from the output clock signal, and a second feedback signal derived from the output clock signal and a parameter α
, the phase frequency detector to provide the first, second, and third logic signals to the charge pump. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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Specification