Signaling system with low-power automatic gain control

• US 7,498,882 B2
• Filed: 04/18/2006
• Issued: 03/03/2009
• Est. Priority Date: 04/18/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Dally, William J., Poulton, John W.
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US11/407,371
• Publication Number:
  US 20070241821A1
• Time in Patent Office: 1,050 Days
• Field of Search: 330/278, 330/279, 330/307
• US Class Current: 330/279
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03K 2005/00039 having four transistors serially

Abstract

An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.

Claims

1. An integrated circuit device comprising:

a variable-gain amplifier to generate an amplified signal having an amplitude according to a gain control value;

a memory circuit to store the gain control value and provide the gain control value to the variable-gain amplifier during a first interval;

an update circuit to generate an updated gain control value based on the amplified signal during the first interval, and to output the updated gain control value to the memory circuit; and

wherein the update circuit comprises an input to receive an inhibit signal, and wherein the update circuit is enabled to generate the updated gain control value when the inhibit signal is in a first state and inhibited from generating the updated gain control value when the inhibit signal is in the second state.

2. The integrated circuit device of claim 1 wherein the gain control value comprises an analog gain control signal and wherein the variable-gain amplifier includes circuitry that amplifies an input signal in accordance with the analog gain control signal to generate the amplified signal.

3. The integrated circuit device of claim 2 wherein the memory circuit comprises a storage element to store a digital control word that corresponds to the analog gain control signal and a digital-to-analog converter to generate the analog gain control signal based on the digital control word.

4. The integrated circuit device of claim 3 wherein the updated gain control value comprises an analog update signal and wherein the memory circuit further comprises an analog-to-digital converter to generate, based on the analog update signal, an updated digital control word to be stored in the storage element and provided to the digital-to-analog converter during an interval subsequent to the first interval.

5. The integrated circuit device of claim 1 wherein the memory circuit includes an input to receive a load-enable indication, a storage element to store the gain control value and load circuitry to load the updated gain control value into the storage element in place of the gain control value in response to the load-enable indication, the integrated circuit device further comprising a control circuit to output the inhibit signal in the first state during the first interval and to generate the load-enable indication at the conclusion of the first interval.

6. The integrated circuit device of claim 5 wherein the control circuit is configured to output the inhibit signal in the second state after conclusion of the first interval.

7. The integrated circuit device of claim 5 wherein the inhibit signal is supplied to the memory circuit as the load-enable indication, and wherein the control circuit is configured to transition the inhibit signal from the first state to the second state to generate the load-enable indication.

8. The integrated circuit device of claim 1 wherein the update circuit comprises a detector to detect an amplitude of the amplified signal and a comparator to compare the amplitude of the amplified signal with a desired amplitude, the comparator having an output to output an error signal that indicates whether the amplitude of the amplified signal exceeds the desired amplitude.

9. The integrated circuit device of claim 8 further comprising a programmable storage circuit to store a value that represents the desired amplitude.

10. The integrated circuit of claim 8 further comprising an analog-to-digital converter to convert the amplified signal into a sequence of digital samples, and wherein the detector comprises a digital detector to detect a peak digital sample of the digital samples, and wherein the comparator comprises a digital comparator circuit to compare the peak digital sample with a digital value that represents the desired amplitude.

11. The integrated circuit device of claim 8 further comprising a programmable storage circuit to store the digital value that represents the desired amplitude.

12. A method of operation within an integrated circuit device, the method comprising:

generating, during a first interval, an amplified signal having an amplitude according to a first gain control value stored within a storage circuit;

generating a second gain control value based on the amplified signal;

storing the second gain control value in the storage circuit in place of the first gain control value at the conclusion of the first interval; and

disabling circuitry used to generate the second gain control value after the second gain control value is stored in the storage circuit.

13. The method of claim 12 wherein generating the second control value based on the amplified signal comprises generating a sequence of digital values that correspond to the amplified signal and generating the second control value based on the sequence of digital values.

14. An integrated circuit device comprising:

means for storing a gain control value;

means for generating, during a first interval, an amplified signal having an amplitude according to a first gain control value stored within the means for storing;

means for generating a second gain control value based on the amplified signal;

means for loading the second gain control value into the means for storing in place of the first gain control value at the conclusion of the first interval; and

means for disabling circuitry used to generate the second gain control value after the second gain control value is stored in the means for storing.

15. Computer-readable media having information embodied therein that includes a description of an integrated-circuit memory device, the information including descriptions of:

a variable-gain amplifier to generate an amplified signal having an amplitude according to a gain control value;

a memory circuit to store the gain control value and provide the gain control value to the variable-gain amplifier during a first interval; and

an update circuit to generate an updated gain control value based on the amplified signal during the first interval, and to output the updated gain control value to the memory circuit; and

wherein the update circuit comprises an input to receive an inhibit signal, and wherein the update circuit is enabled to generate the updated gain control value when the inhibit signal is in a first state and inhibited from generating the updated gain control value when the inhibit signal is in the second state.