Liquid crystal panel and liquid crystal display device having the same

• US 7,499,019 B2
• Filed: 06/29/2005
• Issued: 03/03/2009
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Hyun Joo, Choo, Kyo Seop
• Primary Examiner(s): Awad; Amr
• Assistant Examiner(s): Sherman; Stephen G
• Application Number:
  US11/172,237
• Publication Number:
  US 20060145977A1
• Time in Patent Office: 1,343 Days
• Field of Search: 345/87, 345/204, 345 11- 13, 345/103, 349/149, 349/151
• US Class Current: 345/103
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An LC panel and an LCD device having an LC panel are provided. The LC panel has a display part and a non-display part. Gate lines and data lines are arranged in a matrix on the display part. The gate lines include a first gate line group and a second gate line group. The first gate line group extends from one end of the display part and does not overlap the extending data lines; the second gate line group extends from an opposite end of the display part and overlaps the extending data lines. The disclosed devices and methods of using such allow one to control signal delay times to the first and second gate line groups so as to improve image quality or prevent imaging defects.

Claims

1. An LC panel comprising:

a display part and a non-display part;

the display part having gate lines and data lines arranged thereon, the gate lines having a first gate line group and a second gate line group;

the non-display part, having gate lines and data lines extending from the display part;

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines, wherein capacitance is not generated in the first gate line group; and

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines, wherein capacitance is generated between the overlapping second gate line group and the extending data lines,

wherein the length of the first gate line group is longer than that of the second gate line group and the line resistance of the first gate line group is greater then that of the second gate line group,

wherein a signal delay in the first gate line group is generated by line resistance in the first gate line group and wherein a signal delay in the second gate line group is generated by line resistance in the second gate line group and by capacitance generated between the second gate line group and the extended data lines,

wherein the signal delay generated by the first gate line group is substantially the same as the signal delay generated by the second gate line group.

2. A liquid crystal display device comprising:

an LC panel, the LC panel comprising;

a display part and a non-display part;

the display part having gate lines and data lines arranged thereon, the gate lines having a first gate line group and a second gate line group;

the non-display part, having gate lines and data lines extending from the display part;

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines, wherein capacitance is not generated in the first gate line group;

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines, wherein capacitance is generated between the overlapping second gate line group and the extending data lines;

a data driver electrically connected to the extending data lines; and

a gate driver electrically connected to the extending gate lines, wherein the length of the first gate line group is longer than that of the second gate line group and the line resistance of the first gate line group is greater then that of the second gate line group,

wherein a signal delay in the first gate line group is generated by line resistance in the first gate line group and wherein a signal delay in the second gate line group is generated by line resistance in the second gate line group and by capacitance generated between the second gate line group and the extended data lines, wherein the signal delay generated by the first gate line group is substantially the same as the signal delay generated by the second gate line group.

3. The liquid crystal display device of claim 2, wherein the gate driver is disposed on the LC panel.

4. The liquid crystal display device of claim 2, wherein the data driver is disposed on the LC panel.

5. A method for manufacturing a liquid crystal display device, comprising:

forming a gate lines include a first gate line group and a second gate line group on a substrate;

forming a gate insulating layer on the substrate and the gate lines; and

forming a data lines on the gate insulating layer,

wherein a display part has gate lines and data lines arranged thereon,

wherein a non-display part includes gate lines and data lines extending from the display part,

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines, wherein capacitance is not generated in the first gate line group,

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines, wherein capacitance is generated between the overlapping second gate line group and the extending data lines,

wherein the length of the first gate line group is longer than that of the second gate line group and the line resistance of the first gate line group is greater then that of the second gate line group,

wherein a signal delay in the first gate line group is generated by line resistance in the first gate line group and wherein a signal delay in the second gate line group is generated by line resistance in the second gate line group and by capacitance generated between the second gate line group and the extended data lines,

wherein the signal delay generated by the first gate line group is substantially the same as the signal delay generated by the second gate line group.