Flash memory array using adjacent bit line as source

• US 7,499,329 B2
• Filed: 03/22/2007
• Issued: 03/03/2009
• Est. Priority Date: 05/12/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nazarian, Hagop A.
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/726,585
• Publication Number:
  US 20070165459A1
• Time in Patent Office: 712 Days
• Field of Search: 365/185.17, 365/185.11, 365/185.19
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays

Abstract

A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

Claims

1. A memory array comprising:

a plurality of non-volatile memory cells arranged in rows and columns wherein each column of memory cells is arranged in a plurality of series strings of memory cells, each series string having a top select transistor and a bottom select transistor;

two series coupled intermediate select transistors subdividing each series string of memory cells, a node formed between the two series coupled intermediate select transistors; and

a plurality of bit lines coupled to the columns such that the top select transistor and bottom select transistor of each string are coupled to a first adjacent bit line wherein a second adjacent bit line is coupled to the node.

2. The memory array of claim 1, wherein the first adjacent bit line of a series string of memory cells operates as the second adjacent bit line of an adjacent series string of memory cells.

3. The memory array of claim 1, wherein the two series coupled intermediate select transistors bisect the series strings of memory cells.

4. The memory array of claim 1, wherein the two series coupled intermediate select transistors do not bisect the series strings of memory cells.

5. The memory array of claim 1, wherein the first adjacent bit line operates as a source line while the second adjacent bit line operates as a bit line or vice versa.

6. The memory array of claim 1, wherein each series string of memory cells is comprised of an even number of memory cells.

7. The memory array of claim 1, wherein each series string of memory cells is comprised of an odd number of memory cells.

8. A NAND Flash memory array comprising:

a plurality of non-volatile memory cells arranged in rows and columns wherein each column of memory cells is arranged in a plurality of series strings of memory cells, each series string having a top select transistor and a bottom select transistor;

a plurality of bit lines coupled to the columns such that the top select transistor is coupled to a first adjacent bit line and the bottom select transistor is coupled to a second adjacent bit line;

a first pair of series coupled intermediate select transistors subdividing each series string of memory cells, a first node formed between the first pair of series coupled intermediate select transistors wherein the first node is coupled to the second adjacent bit line; and

a second pair of series coupled intermediate select transistors further subdividing each series string of memory cells between the first pair of series coupled intermediate select transistors and the bottom select transistor, a second node formed between the second pair of series coupled intermediate select transistors wherein the second node is coupled to the first adjacent bit line.

9. The NAND Flash memory array of claim 8, wherein the control gates of the first pair of series coupled intermediate select transistors are coupled together and the control gates of the second pair of series coupled intermediate select transistors are coupled together.

10. The NAND Flash memory array of claim 9, wherein a plurality of select lines are coupled to the control gates of the first and second pair of series coupled intermediate select transistors.

11. The NAND Flash memory array of claim 8, wherein the first adjacent bit line operates as source line while the second adjacent bit line operates as a bit line or vice versa.

12. The NAND Flash memory array of claim 8, wherein the number of memory cells existing between the top select transistor and the first node, the first node and the second node and the second node and the bottom transistor may or may not be equal.

13. A non-volatile memory device comprising:

memory control circuit that controls operations of the memory device; and

a flash memory array comprising;

a plurality of non-volatile memory cells arranged in rows and columns wherein each column of memory cells is arranged in a plurality of series strings of memory cells, each series string having a top select transistor and a bottom select transistor;

two series coupled intermediate select transistors subdividing each series string of memory cells, a node formed between the two series coupled intermediate select transistors; and

a plurality of bit lines coupled to the columns such that the top select transistor and bottom select transistor of each string are coupled to a first adjacent bit line wherein a second adjacent bit line is coupled to the node.

14. The non-volatile memory device of claim 13 wherein bit lines biased at ground potential act as source lines.

15. The non-volatile memory device of claim 13 wherein bit lines biased at Vcc act as bit lines.

16. The non-volatile memory device of claim 13 wherein the first adjacent bit line operates as source line while the second adjacent bit line operates as a bit line or vice versa.

17. An electronic system comprising:

a processor that generates memory control signals;

a memory device coupled to the processor, the device comprising;

a memory array having a plurality of non-volatile memory cells arranged in rows

and columns wherein each column of memory cells is arranged in a plurality of series strings of memory cells, each series string having a top select transistor and a bottom select transistor;

two series coupled intermediate select transistors subdividing each series string of memory cells, a node formed between the two series coupled intermediate select transistors; and

a plurality of bit lines coupled to the columns such that the top select transistor and bottom select transistor of each string are coupled to a first adjacent bit line wherein a second adjacent bit line is coupled to the node.