×

Flash memory array using adjacent bit line as source

  • US 7,499,329 B2
  • Filed: 03/22/2007
  • Issued: 03/03/2009
  • Est. Priority Date: 05/12/2005
  • Status: Active Grant
First Claim
Patent Images

1. A memory array comprising:

  • a plurality of non-volatile memory cells arranged in rows and columns wherein each column of memory cells is arranged in a plurality of series strings of memory cells, each series string having a top select transistor and a bottom select transistor;

    two series coupled intermediate select transistors subdividing each series string of memory cells, a node formed between the two series coupled intermediate select transistors; and

    a plurality of bit lines coupled to the columns such that the top select transistor and bottom select transistor of each string are coupled to a first adjacent bit line wherein a second adjacent bit line is coupled to the node.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×