Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same

• US 7,499,352 B2
• Filed: 05/17/2007
• Issued: 03/03/2009
• Est. Priority Date: 05/19/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Singh, Anant Pratap
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US11/804,098
• Publication Number:
  US 20070268761A1
• Time in Patent Office: 656 Days
• Field of Search: 365/200, 365/225.7, 365/230.06, 365/230.01
• US Class Current: 365/200
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

An integrated circuit device (for example, a logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory)), including (a) a memory cell array having a plurality of memory cells arranged in (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, (c) a memory to store decoded redundant row address data, (d) normal word line drivers, (e) redundant word line drivers, and (f) redundancy address evaluation circuitry to (i) store decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determine whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, to enable the redundant word line drivers. In another aspect, the present inventions are directed to such row redundancy circuitry.

Claims

1. An integrated circuit device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address;

address decoder circuitry to generate decoded row address data in response to an applied row address;

normal word line drivers, coupled to the address decoder circuitry and the plurality of normal rows of memory cells, to responsively enable one or more normal rows of memory cells using the decoded row address data;

redundant word line drivers, coupled to the address decoder circuitry and the redundant row of memory cells, to responsively enable the redundant row of memory cells using the decoded row address data; and

redundancy address evaluation circuitry, coupled to the address decoder circuitry, the normal word line drivers and the redundant word line drivers, to (i) store decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determine whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, enable the redundant word line drivers.

2. The integrated circuit device of claim 1 wherein the redundancy address evaluation circuitry includes a memory to temporarily store the decoded redundant row address data.

3. The integrated circuit device of claim 2 wherein the redundancy address evaluation circuitry further includes a comparator logic circuitry to compare the decoded row address data and the decoded redundant row address data which is temporarily stored in the memory and, in response to a match, to enable the redundant word line drivers and disable the normal word line drivers.

4. The integrated circuit device of claim 2 wherein the memory, in response to a control signal, stores the decoded redundant row address data provided by the address decoder circuitry.

5. The integrated circuit device of claim 2 wherein the memory, in response to a control signal, stores the decoded redundant row address data generated by the address decoder circuitry.

6. The integrated circuit device of claim 1 wherein the redundancy address evaluation circuitry includes a memory to permanently store the decoded redundant row address data.

7. The integrated circuit device of claim 6 wherein the redundancy address evaluation circuitry further includes a comparator logic circuitry to compare the decoded row address data and the decoded redundant row address data which is permanently stared in the memory and, in response to a match, to enable the redundant word line drivers and disable the normal word line drivers.

8. The integrated circuit device of claim 6 wherein the memory, in response to a control signal, stores the decoded redundant row address data provided by the address decoder circuitry.

9. The integrated circuit device of claim 6 wherein the memory, in response to a control signal, stores the decoded redundant row address data generated by the address decoder circuitry.

10. The integrated circuit device of claim 1 further including controller circuitry, coupled to the address decoder circuitry and the redundancy address evaluation circuitry, to generate (i) the redundant row address and (ii) the control signal, wherein in response thereto, the address decoder circuitry generates decoded redundant row address data and the redundancy address evaluation circuitry stores the decoded redundant row address data.

11. The integrated circuit device of claim 1 further including controller circuitry, coupled to the address decoder circuitry and the redundancy address evaluation circuitry, to determine the redundant row address and to generate (i) the redundant row address and (ii) the control signal, wherein in response thereto, the address decoder circuitry generates decoded redundant row address data and the redundancy address evaluation circuitry stores the decoded redundant row address data.

12. The integrated circuit device of claim 1 further including controller circuitry, coupled to the address decoder circuitry and the redundancy address evaluation circuitry, to determine the redundant row address based on detecting one or more bit failures or anticipated bit failures of memory cells of a row of memory cells of the plurality of normal row of memory cells.

13. The integrated circuit device of claim 12 wherein the controller circuitry generates (i) the redundant of row address and (ii) the control signal, wherein in response thereto, the address decoder circuitry generates decoded redundant row address data and the redundancy address evaluation circuitry stores the decoded redundant row address data.

22. The integrated circuit device of claim 1 wherein the redundancy address evaluation circuitry includes means for (i) storing decoded redundant row address data which corresponds to the redundant row address, and (ii) in operation, determining whether the decoded row address data corresponds to the decoded redundant row address data, and, in response thereto, enable the redundant word line drivers.

14. A method of programming a redundant row of memory cells into an integrated circuit device, the integrated circuit device comprising (a) a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, and (c) a redundancy memory, the method comprising:

determining the redundant row address based on detecting one or more bit failures or anticipated bit failures of memory cells of a row of memory cells of the plurality of normal rows of memory cells;

generating a decoded redundant row address data by applying the redundant row address to the address decoder circuitry, wherein the decoded redundant row address data corresponds to the redundant row address;

generating a redundancy program signal; and

storing the decoded redundant row address data in the redundancy memory in response to the redundancy program signal.

15. The method of claim 14 further including temporarily storing the decoded redundant row address data in the redundancy memory in response to the redundancy program signal.

16. A method of operating an integrated circuit device comprising (a) a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns including (i) a plurality of normal rows of memory cells which are associated with and selectable via normal row addresses and (ii) a redundant row of memory cells which is associated with and selectable via a redundant row address, (b) address decoder circuitry to generate decoded row address data in response to an applied row address, (c) a redundancy memory to store decoded redundant row address data, (d) normal word line drivers and (a) redundant word line drivers, the method comprising:

generating the decoded row address data in response to an applied row address;

responsively enabling (i) at least one of the normal rows of memory cells or (ii) the redundant row of memory cells using the decoded row address data; and

determining, during operation, whether the decoded row address data corresponds to the decoded redundant row address data stored in the redundancy memory, and, in response thereto, enabling the redundant word line drivers and disabling the normal word line drivers.

17. The method of claim 16 further including:

generating decoded redundant row address data using the address decoder circuitry, wherein the decoded redundant row address data corresponds to the redundant row address; and

storing the decoded redundant row address data in the redundancy memory in response to a redundancy program signal.

18. The method of claim 16 further including:

determining the redundant row address based on detecting one or more bit failures or anticipated bit failures of memory cells of a row of memory cells of the plurality of normal rows of memory cells;

generating a decoded redundant row address data using the address decoder circuitry, wherein the decoded redundant row address data corresponds to the redundant row address;

generating a redundancy program signal; and

storing the decoded redundant row address data in the redundancy memory in response to a redundancy program signal.

19. The method of claim 16 further including:

generating a decoded redundant row address data using the address decoder circuit, wherein the decoded redundant row address data corresponds to the redundant row address;

generating a redundancy program signal; and

storing the decoded redundant row address data in the redundancy memory in response to a redundancy program signal.

20. The method of claim 16 further including:

generating a decoded redundant row address data using the address decoder circuitry, wherein the decoded redundant row address data which corresponds to the redundant row address ; and

storing the decoded redundant row address data in the redundancy memory.

21. the method of claim 16 further including temporarily storing the decoded redundant row address data in the redundancy memory in response to a redundancy program signal.