Parallel concatenated code with soft-in soft-out interactive turbo decoder

• US 7,499,503 B2
• Filed: 03/26/2007
• Issued: 03/03/2009
• Est. Priority Date: 09/12/2000
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hughes, Thomas A. Jr., Shen, Ba-Zhong, Jones, Christopher R., Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): WANG, TED M
• Application Number:
  US11/728,519
• Publication Number:
  US 20080043878A1
• Time in Patent Office: 708 Days
• Field of Search: 375/298, 375/295, 375/341, 375/262, 375/265, 714/746, 714/701, 714/755
• US Class Current: 375/298
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2966 Turbo codes concatenated with another code, e.g. an outer block code
• CPC Class Codes: H03M 13/2978 Particular arrangement of the component decoders
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/3922 Add-Compare-Select [ACS] operation in forward or backward recursions
• CPC Class Codes: H03M 13/3927 Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
• CPC Class Codes: H03M 13/3972 using sliding window techniques or parallel windows
• CPC Class Codes: H03M 13/3988 for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0065 : Serial concatenated codes
• CPC Class Codes: H04L 1/0066 : Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 : by puncturing
• CPC Class Codes: H04L 1/0071 : Use of interleaving interleaving per se H03M13/27

Abstract

A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

Claims

1. A method for producing a coded signal from a sequence of tuples, the method comprising:

modulo interleaving input tuples in at least one interleaver

encoding the input tuples in an odd encoder and an even encoder;

encoding to interleaved tuples in the odd encoder and to even encoder;

selecting to encoded tuples from each of to odd encoder and to even encoder; and

mapping the selected, encoded tuples using at least one mapping, wherein only encoded tuples corresponding to input tuples having an odd modulo sequence designation are selected from the odd encoder and only encoded tuples corresponding to input tuples having an even modulo sequence designation are selected from the even encoder.

2. The method of claim 1, wherein:

the encoding the interleaved tuples in the odd encoder and the even encoder includes systematic encoding a sequence of N tuples, where N is an integer number.

3. The method of claim 1, wherein:

the encoding the interleaved tuples in the odd encoder and the even encoder includes nonsystematic encoding.

4. The method of claim 1, wherein:

the encoding the interleaved tuples in the odd encoder and the even encoder includes convolutional encoding.

5. The method of claim 1, wherein:

the encoding the interleaved tuples in the odd encoder and the even encoder includes recursive encoding.

6. The method of claim 1, wherein:

the selecting the encoded tuples from each of the odd encoder and the even encoder includes puncturing at least one bit output from at least one of the odd encoder and the even encoder.

7. The method of claim 6, wherein:

the puncturing at least one bit output from at least one of the odd encoder and the even encoder includes substituting at least one uncoded bit for the at least one punctured bit.

8. The method of claim 1, further comprising:

mapping a first selected tuple of the selected tuples to a first constellation whose constellation points have a first mapping; and

mapping a second selected tuple of the selected tuples to a second constellation whose constellation points have a second mapping.

9. The method of claim 1, further comprising:

inverting at least one interleaved tuple of the interleaved tuples before encoding the at least one interleaved tuple in the odd encoder.

10. The method of claim 1, further comprising:

inverting at least one input tuple of the input tuples before encoding the at least one input tuple in the even encoder.

11. The method of claim 1, wherein:

the method is performed within a communication device.

12. The method of claim 1, wherein:

the at least one mapping includes an 8-PSK (Phase Shift Keying) constellation having 8 constellation points;

or

the at least one mapping includes a 16-QAM (Quadrature Amplitude Modulation) constellation having 16 constellation points.

13. The method of claim 1, wherein:

the selecting the encoded tuples from each of the odd encoder and the even encoder includes puncturing at least one bit output from the odd encoder and at least one bit output from the even encoder.

14. The method of claim 1, wherein:

the at least one interleaver includes a first interleaver and a second interleaver;

at least one input tuple of the input tuples includes a first bit and a second bit;

the first interleaver interleaves the first bit; and

the second interleaver interleaves the second bit.

15. An apparatus, comprising:

at least one interleaver implemented to modulo interleave input tuples;

a first encoder implemented to encode the input tuples and the interleaved tuples;

a second encoder implemented to encode the input tuples and the interleaved tuples;

a selector implemented to select encoded tuples from each of the first encoder and the second encoder; and

a mapper implemented to map the selected, encoded tuples using at least one mapping; and

wherein;

only encoded tuples corresponding to input tuples having an odd modulo sequence designation are selected from the first encoder and only encoded tuples corresponding to input tuples having an even modulo sequence designation are selected from the second encoder.

16. The apparatus of claim 15, further comprising:

an inverter implemented to invert at least one interleaved tuple of the interleaved tuples before the first encoder encodes the at least one interleaved tuple.

17. The apparatus of claim 15, further comprising:

an inverter implemented to invert at least one input tuple of the input tuples before the second encoder encodes the at least one input tuple.

18. The apparatus of claim 15, wherein:

the at least one mapping includes an 8-PSK (Phase Shift Keying) constellation having 8 constellation points;

or

the at least one mapping includes a 16-QAM (Quadrature Amplitude Modulation) constellation having 16 constellation points.

19. The apparatus of claim 15, further comprising:

a puncturing module implemented to puncture at least one bit output from at least one of the first encoder and the second encoder.

20. The apparatus of claim 15, further comprising:

a puncturing module implemented to puncture at least one bit output from the first encoder and at least one bit output from the second encoder.