Communication semiconductor integrated circuit device and a wireless communication system

• US 7,499,688 B2
• Filed: 03/26/2007
• Issued: 03/03/2009
• Est. Priority Date: 07/19/2004
• Status: Expired due to Fees

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation), Ttpom Limited
• Inventors: Yamamoto, Satoru, Henshaw, Robert Astel, Osawa, Hirotaka, Uozumi, Toshiya, Kimura, Yasuyuki
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US11/727,216
• Publication Number:
  US 20070164828A1
• Time in Patent Office: 708 Days
• Field of Search: 455/260, 455/76, 455/323, 455/127.4, 375/219, 331/23
• US Class Current: 455/260
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03J 1/005 in a loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04B 1/04 Circuits

Abstract

In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

Claims

1. A semiconductor integrated circuit device for wireless communication, comprising:

a reference oscillation circuit which generates an oscillation signal in accordance with a set value from outside of the semiconductor integrated circuit device;

an intermediate frequency division circuit which generates an intermediate frequency signal by dividing the oscillation signal;

a frequency-division phase-shift circuit which performs frequency-dividing the intermediate frequency signal and generates orthogonal or quadrature signals with their phase being shifted by 90 degrees from each other;

a modulator circuit which receives transmission signals from outside of the semiconductor integrated circuit device and the quadrature signals and outputs modulated signals;

an adder circuit which synthesizes the modulated signals; and

a transmission oscillation circuit which includes a phase detector, a loop filter, a transmission oscillator, a coupler and a mixer and which receives an output of the adder circuit and the oscillation signal and generates a transmission signal;

wherein the reference oscillation circuit includes a reference oscillator which generates a reference oscillation signal, a programmable frequency divider which performs frequency-dividing the oscillation signal in accordance with a frequency division ratio supplied thereto, a phase comparator which detects a phase difference between an output signal of the programmable frequency divider and the reference oscillation signal, a charge pump and a filter which generate a voltage or a current based on the phase difference detected by the phase comparator, and a high frequency oscillator which generates the oscillation signal and which is controlled by the charge pump and the filter,

wherein the semiconductor integrated circuit device further comprises a frequency division ratio generation circuit which generates an integer part I and a fraction part F/G based on band information concerning an externally supplied use frequency band and mode information indicative of whether signal transmission or reception and channel information as to a setup frequency, and for generating the frequency division ratio based on said integer part I and fraction part F/G, and

wherein the frequency division ratio generation circuit is arranged to generate the frequency division ratio of the programmable frequency divider based on the band information, the mode information, the channel information, and externally supplied setup information as to the frequency division ratio of the programmable frequency divider.

2. A semiconductor integrated circuit device according to claim 1, further comprising:

low noise amplifiers which amplify reception signals in respective frequencies of the reception signals;

a reception frequency-division phase-shift circuit which performs frequency-dividing the oscillation signal and generates orthogonal or quadrature signals with their phases being shifted by 90 degrees from each other; and

reception mixers which synthesize outputs of the low noise amplifiers and an output of the reception frequency-division phase-shift circuit.

3. A semiconductor integrated circuit device according to claim 1, wherein the denominator G of said fraction part F/G is arranged to be generated based on any integer as selected from a combination of a plurality of integers prepared in advance in a way corresponding to said band information and said setup information as to the frequency division ratio.

4. A semiconductor integrated circuit device according to claim 3, wherein a value for obtaining the numerator F of said fraction part F/G is arranged to be generated based on any integer as selected from a combination of a plurality of integers prepared in advance in a way corresponding to said band information and said mode information plus said channel information and also based on said setup information as to the frequency division ratio.

5. A semiconductor integrated circuit device according to claim 4, wherein said frequency division ratio generation circuit comprises:

a frequency division ratio calculation circuit for outputting as the integer part I a quotient obtained by dividing said value generated based on any integer as selected from the combination of the plurality of integers prepared in advance in a way corresponding to said band information and said mode information plus said channel information and also said setup information as to the frequency division ratio by the denominator G generated based on said any integer thus selected while outputting a remainder as the numerator F; and

a delta-sigma modulation circuit for using said denominator G and for performing delta-sigma modulation of said numerator F by using said numerator F to thereby generate the fraction part F/G, wherein

the integer part I generated by said frequency division ratio calculation circuit and the fraction part F/G generated by said delta-sigma modulation circuit are combined together and supplied as a frequency division ratio to said programmable frequency divider.

6. A semiconductor integrated circuit device according to claim 5, wherein said delta-sigma modulation circuit includes an adder for adding said numerator F for use as input data and feedback data together, a one-bit quantizer for quantization of an addition result, an arithmetic unit for increasing an output of the quantizer by a factor of a constant number, a subtracter for obtaining a difference between an output of the arithmetic unit and an output of the adder, and delay means for delaying the resultant difference for feedback to said adder.

7. A semiconductor integrated circuit device according to claim 6, wherein said delta-sigma modulation circuit is a delta-sigma modulation circuit of more than two orders.

8. A semiconductor integrated circuit device according to claim 7, wherein the denominator G of said fraction part F/G is an integral multiple of “

65” and

is set to fall within a range of from 1200 to 1700.

9. A semiconductor integrated circuit according to claim 8, wherein said intermediate frequency division circuit is arranged so that the frequency division ratio thereof is externally supplied after selection of a certain one from among a plurality of values prepared in advance, said certain one being appropriate for preventing harmonic wave components of the intermediate frequency signal as frequency-divided by said intermediate frequency division circuit from entering a signal reception frequency band.

10. A semiconductor integrated circuit device according to claim 9, wherein a register capable of externally setting a value which gives decimal number data of the numerator F of said fraction part F/G to be output from said frequency division ratio generation circuit and an arithmetic unit for computing the value being set in the register and said numerator F are provided in correspondence to said delta-sigma modulation circuit.

11. A semiconductor integrated circuit device according to claim 1, wherein the phase detector, loop filter, transmission oscillator, and mixer constitute a PLL circuit, wherein the mixer is arranged to mix together a feedback signal that is extracted by the coupler from the transmission signal and a signal that is obtained by frequency division of the oscillation signal generated by the reference oscillation circuit, to thereby generate a frequency-divided oscillation signal that is input to the phase detector for comparison with the output of the adder circuit.

12. A semiconductor integrated circuit device according to claim 2, further comprising amplifier units arranged to receive and amplify respective outputs of the reception mixers and to output the amplified signals as received I and Q signals.