Mechanism for enabling full data bus utilization without increasing data granularity

• US 7,500,075 B1
• Filed: 04/17/2001
• Issued: 03/03/2009
• Est. Priority Date: 04/17/2001
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Garrett, Billy Jr.
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Dinh; Ngoc V
• Application Number:
  US09/837,307
• Time in Patent Office: 2,877 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

Claims

1. A memory device including an integrated circuit, the integrated circuit comprising:

a set of one or more control ports;

a first memory portion comprising a first plurality of storage cells, said first memory portion to be coupled to a data bus;

a second memory portion comprising a second plurality of storage cells, said second memory portion to be coupled to said data bus; and

an interface coupled to said set of one or more control ports to receive one or more access requests, said interface to access either said first memory portion or said second memory portion in response to receiving a respective access request and according to portion information in the respective access request, each access request comprising a row command and a column command, said interface being configured to receive a complete access request in an amount of time less than or equal to a time required to cycle one of the first and second memory portions once.

2. The memory of claim 1, wherein said first and second memory portions are electrically isolated from each other.

3. The memory of claim 2, wherein said interface is disposed between said first memory portion and said second memory portion to electrically isolate said first memory portion from said second memory portion.

4. The memory of claim 1, wherein said interface is configured to receive concurrently a row command of a first access request to access the first portion and a column command of a second access request to access the second portion.

5. The memory of claim 1, wherein said interface is capable of receiving a row command and a column command in different halves of a clock cycle.

6. The memory of claim 1, wherein said memory is a dynamic memory.

7. The memory of claim 1, wherein said first memory portion further comprises a first set of sense amplifiers, wherein said second memory portion further comprises a second set of sense amplifiers, and wherein said sets of sense amplifiers are electrically isolated from each other such that noise from activating one set of sense amplifiers does not corrupt data loaded in the other set of sense amplifiers.

8. The memory of claim 7, wherein said first and second sets of sense amplifiers are electrically isolated from each other so that activation of said first set of sense amplifiers does not corrupt data loaded in said second set of sense amplifiers.

9. The memory of claim 7, wherein said first and second sets of sense amplifiers are electrically isolated from each other so that said first set of sense amplifiers may be activated while said second set of sense amplifiers are loaded with data to be stored in the second memory portion.

10. The memory of claim 7, wherein said first and second sets of sense amplifiers are electrically isolated from each other to allow said first and second sets of sense amplifiers to be activated in consecutive clock cycles.

11. The memory of claim 1, wherein said one or more access requests include a first access request to access said first memory portion and a second access request to access said second memory portion, wherein said first access request comprises a first row command and said second access request comprises a second row command, and wherein said first and second row commands are received in immediate succession.

12. The memory of claim 1, wherein said one or more access requests include a first access request to access said first memory portion, and a second access request to access said second memory portion, wherein said first access request comprises a first column command, and said second access request comprises a second column command, and wherein said first and second column commands are received in immediate succession.

13. The memory of claim 1, wherein said one or more access requests include a first access request to access said first memory portion, and a second access request to access said second memory portion, wherein said first access request comprises a first row command, and said second access request comprises a second row command, and wherein said first row command and said second row command are received in consecutive clock cycles.

14. The memory of claim 1, wherein said one or more access requests comprises a read request.

15. The memory of claim 14, wherein said interface receives and forwards a first access request to said first memory portion, causing said first memory portion to access a first set of data from said first plurality of storage cells, said first set of data having a size no greater than one base granularity, said first memory portion outputting said first set of data onto said data bus, and wherein said interface receives and forwards a second access request to said second memory portion, causing said second memory portion to access a second set of data from said second plurality of storage cells, said second set of data having a size no greater than one base granularity, said second memory portion outputting said second set of data onto said data bus.

16. The memory of claim 15, wherein said second set of data follows said first set of data onto said data bus such that there is substantially no idle time on said data bus between said first set of data and said second set of data.

17. The memory of claim 1, wherein said one or more access requests comprises a write request.

18. The memory of claim 17, wherein said interface receives and forwards a first access request to said first memory portion, causing said first memory portion to obtain a first set of data from said data bus, said first set of data having a size no greater than one base granularity, said first memory portion storing said first set of data into a subset of said first plurality of storage cells, and wherein said interface receives and forwards a second access request to said second memory portion, causing said second memory portion to obtain a second set of data from said data bus, said second set of data having a size no greater than one base granularity, said second memory portion storing said second set of data into a subset of said second plurality of storage cells.

19. The memory of claim 18, wherein said second set of data follows said first set of data on said data bus such that there is substantially no idle time on said data bus between said first set of data and said second set of data.

20. The memory device of claim 1 wherein the portion information in the respective access request comprises at least one address value.

21. A memory including an integrated circuit, the integrated circuit comprising:

a set of one or more control ports;

a first memory portion comprising a first plurality of storage cells, and a first set of sense amplifiers to be coupled between a data bus and said first plurality of storage cells, said first memory portion capable of being cycled once in an amount of time T;

a second memory portion comprising a second plurality of storage cells, and a second set of sense amplifiers to be coupled between said data bus and said second plurality of storage cells, said second memory portion also capable of being cycled once in said amount of time T; and

an interface coupled to said set of one or more control ports to receive one or more access requests, said interface to access either said first memory portion or said second memory portion in response to receiving a respective access request and according to portion information in the respective access request, said interface being configured to receive at least a first row command in a first access request and a second row command in a second access request in an amount of time X, where X is less than or equal to T;

wherein said first row command causes said first set of sense amplifiers to be activated while said second row command causes said second set of sense amplifiers to be activated.

22. The memory of claim 21 wherein the portion information in the respective access request comprises at least one address value.

23. A method for accessing a memory, comprising:

receiving a first access request on a set of one or more control ports, said first access request comprising a first row command;

in response to said first access request, accessing a first set of storage cells in a first portion of said memory;

receiving a second access request on said set of one or more control ports, said second access request comprising a second row command; and

in response to said second access request, accessing a second set of storage cells in a second portion of said memory;

wherein said first row command and second row command are received within an amount of time not greater than a time required to cycle one of the first and second portions of the memory once.

24. The method of claim 23, wherein said second row command is received immediately after receiving said first row command.

25. The method of claim 23, wherein said first and second row commands are received in consecutive clock cycles.

26. The method of claim 23, wherein said first and second portions are electrically isolated from each other.

27. The method of claim 23, wherein said first portion comprises a first set of sense amplifiers and said second portion comprises a second set of sense amplifiers, the method further comprising activating said first set of sense amplifiers in response to said first access request and activating said second set of sense amplifiers in response to said second access request.

28. The method of claim 27, wherein said first and second sets of sense amplifiers are electrically isolated from each other such that activation of one set of sense amplifiers does not corrupt data in the other set of sense amplifiers.

29. The method of claim 27, wherein said second set of sense amplifiers is activated immediately after said first set of sense amplifiers.

30. The method of claim 27, wherein said first and second sets of sense amplifiers are activated in consecutive clock cycles.

31. The method of claim 23, wherein a respective access request comprises one row command and one column command, and wherein a respective access request is received in an amount of time less than or equal to the time required to cycle one of the first and second memory portions once.

32. The method of claim 31, wherein the first row command in the first access request and a column command in the second access request are received concurrently.

33. The method of claim 31, wherein the row and column commands in a respective access request are received in consecutive clock cycles.

34. The method of claim 23, wherein said first and second access requests are read requests.

35. The method of claim 34, wherein accessing said first set of storage cells in said first portion of said memory comprises:

accessing a first set of data from said first set of storage cells, said first set of data having a size no greater than one base granularity; and

outputting said first set of data onto a data bus.

36. The method of claim 35, wherein accessing said second set of storage cells in said second portion of said memory comprises:

accessing a second set of data from said second set of storage cells, said second set of data having a size no greater than one base granularity; and

outputting said second set of data onto said data bus.

37. The method of claim 36, wherein said second set of data follows said first set of data onto said data bus such that there is substantially no idle time on said data bus between said first set of data and said second set of data.

38. The method of claim 23, wherein said first and second access requests are write requests.

39. The method of claim 38, wherein accessing said first set of storage cells in said first portion of said memory comprises:

obtaining a first set of data from a data bus, said first set of data having a size no greater than one base granularity; and

storing said first set of data into said first set of storage cells.

40. The method of claim 39, wherein accessing said second set of storage cells in said second portion of said memory comprises:

obtaining a second set of data from said data bus, said second set of data having a size no greater than one base granularity; and

storing said second set of data into said second set of storage cells.

41. The method of claim 40, wherein said second set of data follows said first set of data on said data bus such that there is substantially no idle time on said data bus between said first set of data and said second set of data.

42. In a memory system wherein a memory comprises a first portion and a second portion, a method for controlling access to said memory, comprising:

deriving a first access request to access said first portion of said memory, said first access request comprising a first row command;

deriving a second access request to access said second portion of said memory, said second access request comprising a second row command;

sending said first row command to said memory; and

sending said second row command to said memory;

wherein said first row command and said second row command are sent within a time not greater than a time T required to cycle one of the first and second portions of the memory once.

43. The method of claim 42, wherein said second row command is sent immediately after said first row command.

44. The method of claim 42, wherein said first and second row commands are sent in consecutive clock cycles.

45. The method of claim 42, wherein each access request comprises one row command and one column command.

46. The method of claim 45, wherein the row command and the column command of a respective access request are sent to said memory in an amount of time less than or equal to T.

47. The method of claim 46, wherein said second row command and a column command of the first access request are sent concurrently.

48. The method of claim 46, wherein said second row command and a column command of the first access request are sent in different halves of a clock cycle.

49. The method of claim 46, wherein said column command is a first column command associated with said first access request.

50. The method of claim 42, wherein said first and second row commands are sent in consecutive clock cycles.

51. In a memory system wherein a memory device in an integrated circuit is accessible through a memory bus, a method for controlling access to said memory, comprising:

deriving a first access request, said first access request being directed to a first memory portion of said memory device;

sending said first access request to said memory device for processing, said first access request causing first data to be read out of or written into said first memory portion, said first data being of one base granularity in size;

deriving a second access request;

determining whether said second access request is directed to said first memory portion; and

in response to a determination that said second access request is not directed to said first memory portion, sending said second access request to said memory device, said second access request causing second data to be read out of or written into a second memory portion, said second data being of one base granularity in size, wherein said sending of said second access request is timed such that said second data follows said first data on said memory bus with substantially no idle time in between.

52. The method of claim 51, wherein said first access request comprises a first row command and said second access request comprises a second row command, and wherein said first row command and said second row command are sent within a time not greater than a time required to cycle one of said first and second memory portions once.

53. The method of claim 52, wherein said second row command is sent immediately after said first row command.

54. The method of claim 52, wherein said first and second row commands are sent in consecutive clock cycles.

55. The method of claim 51, further comprising:

in response to a determination that said second access request is directed to said first memory portion, sending said second access request to said memory after a minimum amount of time has passed, said minimum amount of time being at least the time required to cycle one memory portion once.

56. A memory system, comprising:

a data bus,

a memory device in an integrated circuit, comprising;

a set of one or more control ports;

a first memory portion comprising a first plurality of storage cells, said first memory portion coupled to said data bus, and capable of being cycled once in an amount of time T;

a second memory portion comprising a second plurality of storage cells, said second memory portion coupled to said data bus, and also capable of being cycled once in said amount of time T; and

an interface coupled to said set of one or more control ports to receive one or more access requests to access either said first memory portion or said second memory portion, each access request comprising a row command and a column command, said interface is configured to receive a complete access request in an amount of time X, where X is less than or equal to T;

and

a controller coupled to said data bus and said set of one or more control ports to control operation of said memory device, said controller configured to send a complete access request in an amount of time that is substantially the same as said amount of time X.

57. The memory system of claim 56, wherein said first and second memory portions are electrically isolated from each other.

58. The memory system of claim 57, wherein said interface is disposed between said first memory portion and said second memory portion to electrically isolate said first memory portion from said second memory portion, and vice versa.

59. The memory system of claim 56, wherein said controller is further configured to:

derive a first access request, said first access request being directed to said first memory portion;

send said first access request to said memory device for processing, said first access request causing first data to be read out of or written into said first memory portion, said first data being of one base granularity in size;

derive a second access request;

determine which memory portion said second access request is directed to; and

send said second access request to said memory in response to a determination that said second access request is directed to said second memory portion, said second access request causing second data to be read out of or written into said second memory portion, said second data being of one base granularity in size, wherein said second access request is sent within such a time after sending said first access request that said second data follows said first data on the memory bus with substantially no idle time in between.

60. The memory system of claim 56, wherein said first access request includes a first row command and said second access request includes a second row command, and wherein said controller sends said first and second row commands within an amount of time that is substantially the same as said amount of time X.

61. The memory system of claim 60, wherein said memory is configured to allow said first and second memory portions to be accessed in consecutive clock cycles.

62. The memory system of claim 60, wherein said controller sends said first and second row commands in consecutive clock cycles.

63. The memory system of claim 62, wherein said memory is configured to allow said first set of sense amplifiers and said second set of sense amplifiers to be activated in consecutive clock cycles.

64. The memory system of claim 56, wherein said first memory portion further comprises a first set of sense amplifiers, and said second memory portion further comprises a second set of sense amplifiers, and wherein said memory device is configured to allow said first set of sense amplifiers to be activated within the time X after said second set of sense amplifiers are activated.

65. The memory system of claim 64, wherein said first and second sets of sense amplifiers are electrically isolated from each other.

66. The memory system of claim 64, wherein said memory is configured to require no minimum time delay between activating said first set of sense amplifiers and activating said second set of sense amplifiers.

67. A memory device in an integrated circuit to be coupled to a data bus, comprising:

a first memory portion comprising a first plurality of storage cells;

a second memory portion comprising a second plurality of storage cells; and

an interface to receive a plurality of access requests, each access request for accessing one of said first and second memory portions and including a column command, said plurality of access requests being timed such that a first column command for accessing said first memory portion and a second column command for accessing said second memory portion are both received by said interface in a time period not longer than an amount of time required to cycle one of the first and second memory portions once.

68. The memory device of claim 67 wherein said amount of time required to cycle one of the first and second memory portions once is substantially equal to an amount of time needed to read one base granularity of data out of said one of the first and second memory portions.

69. The memory device of claim 67 wherein said first and second column command are from first and second read requests and cause first data of one base granularity in size from said first memory portion and second data of one base granularity in size from said second memory portion to be placed on said data bus, said second data follows said first data with substantially no idle time in between.

70. The memory device of claim 67 wherein said first and second column commands are from first and second write requests and cause first data of one base granularity in size from said data bus and second data of one base granularity in size from said data bus to be placed in respective ones of said first and second memory portions, said second data follows said first data on said data bus with substantially no idle time in between.

71. The memory device of claim 67 wherein the first and second column commands are received in consecutive clock cycles.

72. A memory device in an integrated circuit to be coupled to a data bus, comprising:

a first memory portion;

a second memory portion;

an interface to receive access requests and to forward respective access requests to respective ones of said first and second memory portions, said access requests including a first access request causing first data to be read out of or written into said first memory portion and a second access request causing second data to be read out of or written into said second memory portion, said first data being of one base granularity in size, said second data being of one base granularity in size and following said first data on said memory bus with substantially no idle time in between; and

wherein said first access request includes a first column command and said second access request includes a second column command, and wherein said interface is configured to receive both said first and second column commands within a time period not longer than an amount of time required to cycle one of said first and second memory portions once.

73. The memory device of claim 72 wherein said amount of time required to cycle one of the first and second memory portions once is substantially equal to an amount of time needed to read one base granularity of data out of said one of the first and second memory portions.

74. The memory device of claim 72 wherein said first and second column commands are received in consecutive clock cycles.

75. A method performed by a memory device in an integrated circuit coupled to a data bus, comprising:

receiving a first access request at said memory device, said first access request for accessing a first memory portion of said memory device and including a column command;

in response to said first access request, writing first data from said data bus into said first portion of said memory, said first data being of one base granularity in size;

receiving a second access request at said memory device, said second access request for accessing a second memory portion of said memory device and including a second column command; and

in response to said second access request, writing second data from said data bus into said second portion of said memory, said second data being of one base granularity in size;

wherein said first and second column commands are received within such a time period that said second data follows said first data on said data bus with substantially no idle time in between; and

wherein said time period is not longer than an amount of time required to cycle one of the first and second portions of the memory device once.

76. The memory device of claim 75 wherein said amount of time required to cycle one of said first and second memory portions once is substantially equal to an amount of time needed to write one base granularity of data into one of said first and second memory portions.

77. A method performed by a memory device in an integrated circuit coupled to a data bus, comprising:

receiving a first access request;

in response to said first access request, placing first data from a first memory portion of said memory device on said data bus, said first data being of one base granularity in size;

receiving a second access request; and

in response to said second access request, placing second data from a second memory portion of said memory device on said data bus, said second data being of one base granularity in size;

wherein said second data follow said first data on said data bus with substantially no idle time in between; and

wherein said first access request includes a first column command and said second access request includes a second column command, and wherein said first and second column commands are both received by said memory device within a time period not longer than an amount of time required to cycle one of said first and second memory portions once.

78. The method of claim 77 wherein said amount of time required to cycle one of the first and second memory portions once is substantially equal to an amount of time needed to read one base granularity of data out of said one of the first and second memory portions.

79. The method of claim 78 wherein said first and second column commands are received in consecutive clock cycles.

80. A method for accessing an integrated circuit memory device, comprising:

deriving a first access request to access a first memory portion of said memory device, said first access request including a first column command;

deriving a second access request to access a second memory portion of said memory device, said second access request comprising a second column command;

sending said first column command to said memory device; and

sending said second column command to said memory device within such a time after sending said first column command that said first and second column commands are both received by said memory device within a period of time not longer than a time required to cycle one of said first and second memory portions once.

81. The method of claim 80 wherein said memory is coupled to a data bus and wherein said amount of time required to cycle one of the first and second memory portions once is substantially equal to an amount of time needed to place one base granularity of data out of said one of the first and second memory portions onto said data bus.