Identifying code for compilation

• US 7,500,085 B2
• Filed: 07/25/2005
• Issued: 03/03/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Faherty; Corey S
• Application Number:
  US11/188,504
• Publication Number:
  US 20060026405A1
• Time in Patent Office: 1,317 Days
• Field of Search: 712/200, 712/209, 712/211
• US Class Current: 712/209
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed, an instruction from the set causes the clock to increment a counter external to the processor while the subset is processed. A status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.

Claims

1. A processor, comprising:

fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions;

decode logic coupled to the fetch logic and adapted to process the set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set of the processor, each entry in the vector table comprising a first bit that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second bit that indicates whether or not the instruction is to be executed if the micro-sequence is executed; and

a clock coupled to the decode logic;

wherein when the decode logic processes an instruction from the set of instructions and when the first bit in the entry for the instruction indicates the micro-sequence is to be executed, the micro-sequence corresponding to the instruction is executed to enable a counter external to the processor, wherein enabling the counter causes the clock to increment the counter while the subset is processed,

wherein a status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.

2. The processor of claim 1, wherein the efficiency level is indicative of the efficiency with which the decode logic processes the subset of instructions.

3. The processor of claim 1, wherein the clock increments the counter with the passing of each clock cycle.

4. The processor of claim 1, wherein the clock increments the counter with the passing of a unit of time, wherein the unit of time is adjustable.

5. The processor of claim 1, wherein the clock increments the counter each time a memory is accessed to obtain data.

6. The processor of claim 1, wherein the clock increments the counter for each clock cycle that elapses while a memory is accessed to obtain data.

7. The processor of claim 1, wherein said efficiency level is determined by dividing the status of the counter by a number of instructions located in said subset.

8. The processor of claim 1, wherein said efficiency level is compared to that of another subset of instructions to determine which subset is to be compiled.

9. The processor of claim 1, wherein the counter is located in an input-output (I/O) memory space external to the processor.

10. The processor of claim 1, wherein after the subset of instructions is decoded, a micro-sequence corresponding to another instruction in the set of instructions is executed to disable the counter.

11. The processor of claim 1, wherein

when the second bit in the entry for the instruction indicates that the instruction is not to be executed, the micro-sequence is executed in lieu of the instruction and also performs a function of the instruction, and

when the second bit indicates that the instruction is to be executed, the instruction is executed after the micro-sequence is executed.

29. The processor of claim 1, wherein the micro-sequence consists of instructions from a register-based instruction set of the processor and the set of instructions comprises instructions from a stack-based instruction set of the processor.

12. An electronic device, comprising:

a decode logic adapted to process a set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set, each entry in the vector table comprising a first field that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second field that indicates whether or not the instruction is to be executed if the micro-sequence is executed;

a clock coupled to the decode logic; and

a memory coupled to the decode logic and comprising a counter;

wherein the decode logic is further adapted to process an instruction, wherein the micro-sequence corresponding to the instruction is executed to enable the counter when the first field in the entry for the instruction indicates the micro-sequence is to be executed, wherein enabling the counter causes the clock to increment the counter with each clock pulse, the counter incremented only while the set of instructions is processed,

wherein a status of the counter is manipulated to determine an efficiency level pertaining to the set of instructions.

13. The electronic device of claim 12, wherein the efficiency level is indicative of the efficiency with which the decode logic processes the set of instructions.

14. The electronic device of claim 12, wherein the device is at least one of a mobile communication device or a battery-operated device.

15. The electronic device of claim 12, wherein the counter is located in an input-output (I/O) space of the memory.

16. The electronic device of claim 12, wherein the decode logic is further adapted to process another instruction after the set of instructions is decoded, wherein a micro-sequence corresponding to the another instruction is executed to disable the counter.

17. The electronic device of claim 12, wherein

when the second field in the entry for the instruction indicates that the instruction is not to be executed, the micro-sequence is executed in lieu of the instruction and also performs a function of the instruction, and

when the second field indicates that the instruction is to be executed, the instruction is executed after the micro-sequence is executed.

18. The electronic device of claim 12, wherein the efficiency level is determined by dividing the status of the counter by the number of instructions in the set of instructions.

19. The electronic device of claim 12, wherein the clock increments the counter with the passing of a clock cycle.

20. The electronic device of claim 12, wherein the clock increments the counter such that the status of the counter reflects a length of time.

21. The electronic device of claim 12, wherein the clock increments the counter when the memory is accessed to obtain data.

22. The electronic device of claim 12, wherein the clock increments the counter when a clock cycle elapses while the memory is accessed to obtain data.

30. The electronic device of claim 12, wherein the micro-sequence consists of instructions from a register-based instruction set and the set of instructions comprises instructions from a stack-based instruction set.

23. A method, comprising:

decoding an instruction, wherein a micro-sequence corresponding to the instruction is executed when a first field in an entry of a decoder vector table corresponding to the instruction indicates that the micro-sequence is to be executed, wherein the micro-sequence enables a counter external to a processor, wherein enabling the counter causes a processor clock to increment the counter while instructions are processed, and wherein when a second field in the entry indicates that the instruction is not be executed, the micro-sequence also performs a function of the instruction, and when the second field indicates that the instruction is to be executed, the instruction is executed after the micro-sequence is executed;

processing a first set of instructions, wherein the counter is incremented only while the first set of instructions is processed;

after the first set of instructions has been processed, manipulating a status of the counter to determine an efficiency level pertaining to the first set of instructions; and

comparing said efficiency level to that of a second set of instructions to determine which of the first set or the second set is to be compiled.

24. The method of claim 23, wherein determining the efficiency level comprises determining the efficiency with which the first set of instructions is processed.

25. The method of claim 23, wherein causing the processor clock to increment the counter comprises incrementing the counter only when a clock cycle elapses.

26. The method of claim 23, wherein causing the processor clock to increment the counter comprises incrementing the counter only at regular intervals, said intervals selected from the group consisting of minutes, seconds, milliseconds, microseconds and nanoseconds.

27. The method of claim 23, wherein causing the processor clock to increment the counter comprises incrementing the counter only when a memory is accessed to obtain data.

28. The method of claim 23, wherein causing the processor clock to increment the counter comprises incrementing the counter only when a clock cycle elapses while a memory is accessed to obtain data.