Power MOSFET and method for forming same using a self-aligned body implant

• US 7,501,323 B2
• Filed: 04/12/2005
• Issued: 03/10/2009
• Est. Priority Date: 07/20/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Au; Bac H
• Application Number:
  US11/104,164
• Publication Number:
  US 20050184318A1
• Time in Patent Office: 1,428 Days
• Field of Search: 438/257, 438/259, 438268-272
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

Claims

1. A method for making a MOSFET comprising:

forming a trench in a semiconductor layer;

forming a gate dielectric layer lining the trench;

forming a gate conducting layer in a lower portion of the trench;

forming a dielectric layer to fill an upper portion of the trench;

removing portions of the semiconductor layer laterally adjacent the dielectric layer so that an upper portion thereof extends outwardly from the semiconductor layer;

forming source regions in the semiconductor layer adjacent the outwardly extending dielectric layer;

forming spacers laterally adjacent the outwardly extending upper portion of the dielectric layer after forming the source regions;

using the spacers as a self-aligned mask for forming source/body contact regions in the semiconductor layer so that the source/body contacts regions are below the source regions;

forming a source electrode on the source regions and on the dielectric layer; and

forming at least one conductive via between the source electrode and the source/body contact regions.

2. A method according to claim 1, wherein using the spacers as a self-aligned mask comprises implanting dopants for defining the source/body contact regions.

3. A method according to claim 1, wherein using the spacers as a self-aligned mask comprises etching the semiconductor layer not covered by the spacers.

4. A method according to claim 3, wherein the etching is performed to a depth equal to or less than about 1 micron from a surface of the semiconductor layer.

5. A method according to claim 1, further comprising removing the spacers.

6. A method according to claim 1, wherein removing portions of the semiconductor layer is performed to a depth equal to or less than about 1 micron from a surface thereof.

7. A method according to claim 1, wherein the gate conducting layer is recessed in the trench within a range of about 0.2 to 0.8 microns from an opening thereof.

8. A method according to claim 1, further comprising forming a body in the semiconductor layer adjacent the trench.

9. A method for making a MOSFET comprising:

forming a trench in a semiconductor layer;

forming a gate dielectric layer lining the trench;

forming a gate conducting layer in a lower portion of the trench;

forming a dielectric layer to fill an upper portion of the trench;

removing portions of the semiconductor layer laterally adjacent the dielectric layer so that an upper portion thereof extends outwardly from the semiconductor layer;

forming spacers laterally adjacent the outwardly extending upper portion of the dielectric layer after forming the source regions;

using the spacers as a self-aligned mask for etching the semiconductor layer not covered by the spacers;

using the spacers as a self-aligned mask for implanting dopants for defining source/body contact regions in the semiconductor layer so that the source/body contacts regions are below the source regions;

forming a source electrode on the source regions and on the dielectric layer; and

forming at least one conductive via between the source electrode and the source/body contact regions.

10. A method according to claim 9, wherein the etching is performed to a depth equal to or less than about 1 micron from a surface of the semiconductor layer.

11. A method according to claim 9, further comprising removing the spacers.

12. A method according to claim 9, wherein removing portions of the semiconductor layer is performed to a depth equal to or less than about 1 micron from a surface

13. A method according to claim 9, wherein the gate conducting layer is recessed in the trench within a range of about 0.2 to 0.8 microns from an opening thereof.

14. A method according to claim 9, further comprising forming a body region in the semiconductor layer adjacent the trench.